Simulation Results: rv_dm/use_dmi_interface

 
25/03/2026 16:05:50 DVSim: v1.16.0 sha: 03992b6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.60 %
  • code
  • 73.93 %
  • assert
  • 96.24 %
  • func
  • 86.62 %
  • line
  • 90.32 %
  • branch
  • 75.85 %
  • cond
  • 76.18 %
  • toggle
  • 71.03 %
  • FSM
  • 56.25 %
Validation stages
V1
96.77%
V2
75.00%
V2S
66.67%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 3.160s 0.000us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.460s 0.000us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.830s 0.000us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 8.920s 0.000us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 3.130s 0.000us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 1.730s 0.000us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 3.120s 0.000us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 25.830s 0.000us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 110.540s 0.000us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 2.540s 0.000us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.150s 0.000us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.800s 0.000us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.850s 0.000us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.940s 0.000us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.040s 0.000us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.760s 0.000us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.170s 0.000us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 2.540s 0.000us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.760s 0.000us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.710s 0.000us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.800s 0.000us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.860s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.410s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 2.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 50.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 19.820s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 2.220s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 19.820s 0.000us 1 1 100.00
rv_dm_csr_rw 2.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.850s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.870s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 3.160s 0.000us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.730s 0.000us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 1.160s 0.000us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.010s 0.000us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 3.440s 0.000us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 254.530s 0.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 273.460s 0.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 145.050s 0.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 156.450s 0.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.860s 0.000us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 3.010s 0.000us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.260s 0.000us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.770s 0.000us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm_rand_reset 39.510s 0.000us 1 1 100.00
rv_dm_tap_fsm 11.510s 0.000us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.800s 0.000us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 4.490s 0.000us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.810s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 2.780s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 2.780s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 19.820s 0.000us 1 1 100.00
rv_dm_csr_hw_reset 1.410s 0.000us 1 1 100.00
rv_dm_csr_rw 2.000s 0.000us 1 1 100.00
rv_dm_same_csr_outstanding 3.400s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 19.820s 0.000us 1 1 100.00
rv_dm_csr_hw_reset 1.410s 0.000us 1 1 100.00
rv_dm_csr_rw 2.000s 0.000us 1 1 100.00
rv_dm_same_csr_outstanding 3.400s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 12.770s 0.000us 1 1 100.00
rv_dm_sec_cm 3.200s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 12.770s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 3.010s 0.000us 1 1 100.00
rv_dm_debug_disabled 0.800s 0.000us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 3.010s 0.000us 1 1 100.00
rv_dm_debug_disabled 0.800s 0.000us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 3.160s 0.000us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 0.820s 0.000us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.830s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.830s 0.000us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 0.820s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rv_dm_stress_all_with_rand_reset 18.810s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 162.460s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 4525055730607186049137705329504023697613189436862421131933370085730982996741 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 65170367310819907235326843117843381639340607867545894872513257076457487675639 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 103368710674611894824299731510981970552250154899268611181023120233531712331940 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 45864748213285073739637428352908627917196517497491579639451925464749131460750 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 30813374964339632912538342266118357152560856769147945985170306900677854493988 77
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 84551839262012779945450072639137776022591912423712233630854985896965458842574 77
UVM_ERROR @ 89811817 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 89811817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 53469417523599347586136706148511555787097706551168511191549491026391871242845 87
UVM_ERROR @ 6863577600 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6863577600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 37307882710398344608185670300225854807440585406751172465196393968080835045657 77
UVM_ERROR @ 295668714 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 295668714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 18031222499459039896342943500620222054833838216059202140187554140138633669518 77
UVM_ERROR @ 510290808 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (429398604 [0x19981a4c] vs 0 [0x0])
UVM_INFO @ 510290808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
rv_dm_debug_disabled 106888101152073890344945401505191178982920045923573069567430395375221475686751 80
UVM_ERROR @ 19120545 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 19120545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])
rv_dm_buffered_enable 60672041792802484644558564492082775760328727320893956242739805614586422314202 83
UVM_ERROR @ 194949485 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 194949485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---