Simulation Results: spi_host

 
25/03/2026 16:05:50 DVSim: v1.16.0 sha: 03992b6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.93 %
  • code
  • 94.90 %
  • assert
  • 95.64 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 93.05 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 44.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 3.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 1.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 3.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 3.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 7.000s 0.000us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 8.000s 0.000us 1 1 100.00
spi_host_error_cmd 7.000s 0.000us 1 1 100.00
spi_host_event 11.000s 0.000us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 9.000s 0.000us 1 1 100.00
speed 1 1 100.00
spi_host_speed 9.000s 0.000us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 9.000s 0.000us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 8.000s 0.000us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 6.000s 0.000us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 9.000s 0.000us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 9.000s 0.000us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 44.000s 0.000us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 44.000s 0.000us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 24.000s 0.000us 1 1 100.00
spien 1 1 100.00
spi_host_spien 11.000s 0.000us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 43.000s 0.000us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 7.000s 0.000us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 8.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 4.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 4.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 5.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 5.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 3.000s 0.000us 1 1 100.00
spi_host_csr_rw 1.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 1.000s 0.000us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 3.000s 0.000us 1 1 100.00
spi_host_csr_rw 1.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 1.000s 0.000us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 5.000s 0.000us 1 1 100.00
spi_host_tl_intg_err 4.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 4.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_host_upper_range_clkdiv 169.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 867038066044903320997334868948511287131347206390069402333669709408469585835 156
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---