Simulation Results: sram_ctrl/ret

 
25/03/2026 16:05:50 DVSim: v1.16.0 sha: 03992b6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.31 %
  • code
  • 91.56 %
  • assert
  • 95.65 %
  • func
  • 95.73 %
  • line
  • 97.96 %
  • branch
  • 95.96 %
  • cond
  • 92.29 %
  • toggle
  • 90.66 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.620s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.900s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.010s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.760s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.490s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.340s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 223.770s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 214.340s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 28.070s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 250.450s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.050s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 486.770s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.590s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 350.420s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 15.190s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.710s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 6.140s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 51.180s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.970s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1309.220s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.850s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.290s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.290s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.900s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.900s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.540s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.470s 0.000us 1 1 100.00
sram_ctrl_sec_cm 1.110s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 1.110s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.470s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 51.180s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 51.180s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 486.770s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 486.770s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 486.770s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.050s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.030s 0.000us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.540s 0.000us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.330s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.620s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.620s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 486.770s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 1.110s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.050s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 1.110s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.110s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.620s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.110s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 22.680s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 44441588295094709818630930214254873323421574973910935212425383438057342010858 105
UVM_ERROR @ 19361541 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 19361541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---