Simulation Results

Simulation Results: uart

25/03/2026 16:05:50 DVSim: v1.16.0 sha: 03992b6 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.67 %

code
95.84 %

assert
97.12 %

func
52.05 %

line
99.17 %

branch
97.44 %

cond
95.22 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		97.06%
V2S		100.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	0.810s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.610s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.630s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.120s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.880s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.740s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.630s	0.000us	1	1	100.00
	uart_csr_aliasing	0.880s	0.000us	1	1	100.00

33/34 passed

97.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	10.990s	0.000us	1	1	100.00
parity				2	2	100.00
	uart_smoke	0.810s	0.000us	1	1	100.00
	uart_tx_rx	10.990s	0.000us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	3.820s	0.000us	1	1	100.00
	uart_rx_parity_err	38.210s	0.000us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	10.990s	0.000us	1	1	100.00
	uart_intr	3.820s	0.000us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	11.630s	0.000us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	30.030s	0.000us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	17.410s	0.000us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	3.820s	0.000us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	3.820s	0.000us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	3.820s	0.000us	1	1	100.00
perf				1	1	100.00
	uart_perf	90.320s	0.000us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	1.800s	0.000us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	1.800s	0.000us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	2.940s	0.000us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	2.450s	0.000us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.770s	0.000us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	11.070s	0.000us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	317.960s	0.000us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	124.310s	0.000us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.580s	0.000us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.550s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.390s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.390s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.610s	0.000us	1	1	100.00
	uart_csr_rw	0.630s	0.000us	1	1	100.00
	uart_csr_aliasing	0.880s	0.000us	1	1	100.00
	uart_same_csr_outstanding	0.720s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.610s	0.000us	1	1	100.00
	uart_csr_rw	0.630s	0.000us	1	1	100.00
	uart_csr_aliasing	0.880s	0.000us	1	1	100.00
	uart_same_csr_outstanding	0.720s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.840s	0.000us	1	1	100.00
	uart_tl_intg_err	1.250s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.250s	0.000us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	19.110s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *
	uart_noise_filter	3504867581023013174808114998304545838226616914123106985249594654800626010954	74	UVM_ERROR @ 1190616787 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1190616787 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 2090290651 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 2 UVM_ERROR @ 2090332318 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2090707321 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 204 [0xcc]) reg name: uart_reg_block.rdata