Simulation Results: hmac

 
26/03/2026 16:02:32 DVSim: v1.16.0 sha: a1ef9e2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.68 %
  • code
  • 98.38 %
  • assert
  • 96.70 %
  • func
  • 43.96 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.940s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.800s 0.000us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.850s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.100s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.180s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.370s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.850s 0.000us 1 1 100.00
hmac_csr_aliasing 2.180s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 11.550s 0.000us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 67.700s 0.000us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.800s 0.000us 1 1 100.00
hmac_test_sha384_vectors 18.540s 0.000us 1 1 100.00
hmac_test_sha512_vectors 382.610s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 8.410s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 8.790s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 8.920s 0.000us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.180s 0.000us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 179.890s 0.000us 1 1 100.00
error 1 1 100.00
hmac_error 48.460s 0.000us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 81.860s 0.000us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.940s 0.000us 1 1 100.00
hmac_long_msg 11.550s 0.000us 1 1 100.00
hmac_back_pressure 67.700s 0.000us 1 1 100.00
hmac_datapath_stress 179.890s 0.000us 1 1 100.00
hmac_burst_wr 8.180s 0.000us 1 1 100.00
hmac_stress_all 173.150s 0.000us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.940s 0.000us 1 1 100.00
hmac_long_msg 11.550s 0.000us 1 1 100.00
hmac_back_pressure 67.700s 0.000us 1 1 100.00
hmac_datapath_stress 179.890s 0.000us 1 1 100.00
hmac_wipe_secret 81.860s 0.000us 1 1 100.00
hmac_test_sha256_vectors 7.800s 0.000us 1 1 100.00
hmac_test_sha384_vectors 18.540s 0.000us 1 1 100.00
hmac_test_sha512_vectors 382.610s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 8.410s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 8.790s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 8.920s 0.000us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.940s 0.000us 1 1 100.00
hmac_long_msg 11.550s 0.000us 1 1 100.00
hmac_back_pressure 67.700s 0.000us 1 1 100.00
hmac_datapath_stress 179.890s 0.000us 1 1 100.00
hmac_burst_wr 8.180s 0.000us 1 1 100.00
hmac_error 48.460s 0.000us 1 1 100.00
hmac_wipe_secret 81.860s 0.000us 1 1 100.00
hmac_test_sha256_vectors 7.800s 0.000us 1 1 100.00
hmac_test_sha384_vectors 18.540s 0.000us 1 1 100.00
hmac_test_sha512_vectors 382.610s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 8.410s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 8.790s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 8.920s 0.000us 1 1 100.00
hmac_stress_all 173.150s 0.000us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 173.150s 0.000us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.530s 0.000us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.940s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.940s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.800s 0.000us 1 1 100.00
hmac_csr_rw 0.850s 0.000us 1 1 100.00
hmac_csr_aliasing 2.180s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.410s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.800s 0.000us 1 1 100.00
hmac_csr_rw 0.850s 0.000us 1 1 100.00
hmac_csr_aliasing 2.180s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.410s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 0.000us 1 1 100.00
hmac_tl_intg_err 2.300s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.300s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.940s 0.000us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.900s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 55.660s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.850s 0.000us 1 1 100.00