Simulation Results: i2c

 
26/03/2026 16:02:32 DVSim: v1.16.0 sha: a1ef9e2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.53 %
  • code
  • 81.70 %
  • assert
  • 95.98 %
  • func
  • 81.92 %
  • line
  • 96.51 %
  • branch
  • 92.48 %
  • cond
  • 85.42 %
  • toggle
  • 89.45 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 48.950s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 23.760s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.680s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.620s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.420s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.730s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.620s 0.000us 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.900s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.720s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 355.080s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.660s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 99.240s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 25.340s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.980s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 9.180s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 6.180s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 71.640s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 17.990s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.740s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.810s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 22.320s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.680s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 11.380s 0.000us 1 1 100.00
i2c_target_intr_smoke 3.990s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.140s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 0.710s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 19.120s 0.000us 1 1 100.00
i2c_target_stress_rd 11.380s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 2.570s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 3.910s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 12.270s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.980s 0.000us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.570s 0.000us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.320s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.010s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 355.080s 0.000us 1 1 100.00
i2c_host_perf_precise 2.090s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 17.990s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 5.790s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.920s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.910s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.020s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.750s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.400s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.600s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.720s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.780s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.780s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.680s 0.000us 1 1 100.00
i2c_csr_rw 0.620s 0.000us 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.950s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.680s 0.000us 1 1 100.00
i2c_csr_rw 0.620s 0.000us 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.950s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.850s 0.000us 1 1 100.00
i2c_tl_intg_err 1.690s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.690s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 11.600s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.820s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 26.700s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 84712436190160827256574608552504995177180497120575102679673291785853504978774 86
UVM_ERROR @ 19179604 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 19179604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 1008464659216648394468891507011690870831275504111597494209514924194186860244 92
UVM_ERROR @ 154508473 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 154508473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 5858304051483749296098549024468575612520162982181385985044141779677980973783 84
UVM_ERROR @ 1819316189 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1819316189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 103755553273129630536713630649806390664955169808566221980697418821307180532890 78
UVM_ERROR @ 262211354 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 262211354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 7471620370864324649740708286894827072957290664214547629715898812400870483388 90
UVM_ERROR @ 983881002 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 983881002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
i2c_target_stress_all_with_rand_reset 49636813847224548178569001513462857885595981884533093343160376740239756438870 99
UVM_ERROR @ 1105479928 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1105479928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_mode_toggle 80360468823189886464979525904456537785468999524377652629157125663745787523447 85
UVM_ERROR @ 169825416 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @47189