Simulation Results: keymgr

 
26/03/2026 16:02:32 DVSim: v1.16.0 sha: a1ef9e2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.42 %
  • code
  • 93.77 %
  • assert
  • 97.72 %
  • func
  • 61.76 %
  • line
  • 98.60 %
  • branch
  • 97.35 %
  • cond
  • 94.04 %
  • toggle
  • 95.16 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 3.500s 0.000us 1 1 100.00
random 1 1 100.00
keymgr_random 2.450s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.170s 0.000us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.520s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 9.060s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.260s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.490s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.520s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.260s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 10.040s 0.000us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.030s 0.000us 1 1 100.00
keymgr_sideload_kmac 2.800s 0.000us 1 1 100.00
keymgr_sideload_aes 1.450s 0.000us 1 1 100.00
keymgr_sideload_otbn 2.560s 0.000us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 5.900s 0.000us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.350s 0.000us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.430s 0.000us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.980s 0.000us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.280s 0.000us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.370s 0.000us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 12.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.930s 0.000us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.920s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.290s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.290s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.170s 0.000us 1 1 100.00
keymgr_csr_rw 1.520s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.260s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 2.400s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.170s 0.000us 1 1 100.00
keymgr_csr_rw 1.520s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.260s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 2.400s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 3.330s 0.000us 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.810s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.810s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.810s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.810s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.760s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.330s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.810s 0.000us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 10.040s 0.000us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 1.520s 0.000us 1 1 100.00
keymgr_random 2.450s 0.000us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 1.520s 0.000us 1 1 100.00
keymgr_random 2.450s 0.000us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 1.520s 0.000us 1 1 100.00
keymgr_random 2.450s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.350s 0.000us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.280s 0.000us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.280s 0.000us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.450s 0.000us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.050s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.130s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.350s 0.000us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.130s 0.000us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.130s 0.000us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.130s 0.000us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 0.000us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.130s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.100s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 94032262071683786668856310648034492155809518536290150859277213032259455978572 435
UVM_ERROR @ 404985991 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 404985991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---