Simulation Results: mbx

 
26/03/2026 16:02:32 DVSim: v1.16.0 sha: a1ef9e2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.39 %
  • code
  • 90.19 %
  • assert
  • 96.96 %
  • func
  • 78.02 %
  • block
  • 95.99 %
  • line
  • 95.47 %
  • branch
  • 89.37 %
  • toggle
  • 85.73 %
Validation stages
V1
87.50%
V2
81.25%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 35.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 145.000s 0.000us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 8.000s 0.000us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 24.000s 0.000us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 13.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 0.000us 1 1 100.00
mbx_csr_rw 1.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 0.000us 1 1 100.00
mbx_csr_rw 1.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 5.000s 0.000us 1 1 100.00
mbx_tl_intg_err 2.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress_zero_delays 41748972477930638404348228844842269030200033519902301164000512708683682339003 121
UVM_ERROR @ 331207130 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (1873203231 [0x6fa6d01f] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 331207130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 48627735479989847031597245833483312815468865822348536337883731090188243349475 85
UVM_ERROR @ 13581800 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15919) { a_addr: 'h6564afb0 a_data: 'he7859acb a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h79 a_opcode: 'h1 a_user: 'h2702c d_param: 'h0 d_source: 'h79 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 13581800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 65726686989114071336180478579277907082213629156574535646804255611456360654591 86
UVM_ERROR @ 2522126 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15825) { a_addr: 'hd31aa94 a_data: 'hfab6a6a0 a_mask: 'he a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h1 a_user: 'h256b6 d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2522126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---