Simulation Results

Simulation Results: rv_dm/use_dmi_interface

26/03/2026 16:02:32 DVSim: v1.16.0 sha: a1ef9e2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.32 %

code
73.40 %

assert
96.16 %

func
86.41 %

line
90.27 %

branch
74.79 %

cond
76.46 %

toggle
69.25 %

FSM
56.25 %

Validation stages

V1		96.77%
V2		75.00%
V2S		83.33%
V3		0.00%
unmapped		0.00%

30/31 passed

96.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	1.790s	0.000us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.150s	0.000us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	0.680s	0.000us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	30.360s	0.000us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	0.780s	0.000us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	4.920s	0.000us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	18.970s	0.000us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	6.980s	0.000us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	139.580s	0.000us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.460s	0.000us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	0.830s	0.000us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	1.290s	0.000us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.670s	0.000us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	1.190s	0.000us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	0.930s	0.000us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.680s	0.000us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.160s	0.000us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.460s	0.000us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.730s	0.000us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	0.800s	0.000us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	1.290s	0.000us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.810s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	2.020s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.260s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	34.970s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	46.180s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	1.640s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	46.180s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.260s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.700s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.750s	0.000us	1	1	100.00

21/28 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	1.790s	0.000us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	0.800s	0.000us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.680s	0.000us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	0.620s	0.000us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	3.160s	0.000us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	124.980s	0.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	67.290s	0.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	148.930s	0.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	60.190s	0.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.690s	0.000us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	2.320s	0.000us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.090s	0.000us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.830s	0.000us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm_rand_reset	40.230s	0.000us	1	1	100.00
	rv_dm_tap_fsm	6.430s	0.000us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.750s	0.000us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	3.310s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.670s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	3.720s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	3.720s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	46.180s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	2.020s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.260s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	2.790s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	46.180s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	2.020s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.260s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	2.790s	0.000us	1	1	100.00

V2S

10/12 passed

83.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_tl_intg_err	6.200s	0.000us	1	1	100.00
	rv_dm_sec_cm	3.140s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	6.200s	0.000us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	2.320s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.730s	0.000us	0	1	0.00
sec_cm_lc_dft_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	2.320s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.730s	0.000us	0	1	0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	1.790s	0.000us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	1.290s	0.000us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.850s	0.000us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.850s	0.000us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	1.290s	0.000us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	16.290s	0.000us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	272.670s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	102195390906970940391834976159995720844280632460771279560012789684448889555145	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	95419798159008532404962501845621665210818234163389058953499258437989133103060	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	35816373823002749192663248607961572789575991073577047890360076730869614431113	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	26463662693690668368133872333814401452859029366237230672676485657274059710919	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	46373695326385121950940362909447004855960595265131587198263338414687004204388	77	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	90006932328900628335042377401624529431651753940267394991443268681431255692710	77	UVM_ERROR @ 63021682 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 63021682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	77741082279701103107796096975848577927856438015642714509576932798341372678620	82	UVM_ERROR @ 1502501690 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 1502501690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	10772092515446842416657191431919697052166122017521092403019158033046237696905	77	UVM_ERROR @ 435922019 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 435922019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	99805953401048205740611528469028038232151699890688108223634937479818720414081	77	UVM_ERROR @ 258426700 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (322297738 [0x1335df8a] vs 0 [0x0]) UVM_INFO @ 258426700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:446) [scoreboard] Check failed (item.d_error)
	rv_dm_debug_disabled	97334907387361062274733744181853087875598230042917949098830771750371462683341	80	UVM_ERROR @ 82027006 ps: (rv_dm_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed (item.d_error) UVM_INFO @ 82027006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
	rv_dm_stress_all_with_rand_reset	77956886034242220871913822551506888378364219426701870209187567759917408453557	118	UVM_FATAL @ 2954624493 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done) UVM_INFO @ 2954624493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---