Simulation Results: sram_ctrl/main

 
26/03/2026 16:02:32 DVSim: v1.16.0 sha: a1ef9e2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.69 %
  • code
  • 89.97 %
  • assert
  • 95.55 %
  • func
  • 95.55 %
  • line
  • 97.50 %
  • branch
  • 94.80 %
  • cond
  • 90.70 %
  • toggle
  • 90.65 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.870s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.690s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.690s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.150s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.500s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.690s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 253.850s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 92.580s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 82.980s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 130.370s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1088.810s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 23.900s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 66.020s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 454.420s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 15.890s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 246.210s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 14.790s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 58.320s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 3.870s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 345.490s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.330s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1973.280s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.630s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.040s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.040s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.690s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.690s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.830s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.690s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.690s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.830s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.180s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.760s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 1.340s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.760s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.340s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 345.490s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 345.490s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.690s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 454.420s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 454.420s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 454.420s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 66.020s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.980s 0.000us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.180s 0.000us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 7.480s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.870s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.870s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 454.420s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.760s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 66.020s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.760s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.760s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.870s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.760s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 25.880s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 8110847562778401087245044480129804928067848775117209614763925955456717852678 98
UVM_ERROR @ 5066193387 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x52) != exp (0x7f)
UVM_INFO @ 5066193387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 52147365720698126097215810092479939027241128719252124470626295600481335348639 99
UVM_ERROR @ 3776229 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3776229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---