| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
70.83% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 21.020s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.720s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.790s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 1.210s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 0.680s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 1.320s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sram_ctrl_csr_rw | 0.790s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.680s | 0.000us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_walk | 6.140s | 0.000us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_partial_access | 2.760s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 1 | 1 | 100.00 | |||
| sram_ctrl_multiple_keys | 437.680s | 0.000us | 1 | 1 | 100.00 | |
| stress_pipeline | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_pipeline | 204.020s | 0.000us | 1 | 1 | 100.00 | |
| bijection | 1 | 1 | 100.00 | |||
| sram_ctrl_bijection | 17.900s | 0.000us | 1 | 1 | 100.00 | |
| access_during_key_req | 1 | 1 | 100.00 | |||
| sram_ctrl_access_during_key_req | 172.620s | 0.000us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 6.350s | 0.000us | 1 | 1 | 100.00 | |
| executable | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 340.610s | 0.000us | 1 | 1 | 100.00 | |
| partial_access | 2 | 2 | 100.00 | |||
| sram_ctrl_partial_access | 4.590s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_partial_access_b2b | 264.840s | 0.000us | 1 | 1 | 100.00 | |
| max_throughput | 3 | 3 | 100.00 | |||
| sram_ctrl_max_throughput | 2.730s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 18.850s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_readback | 60.920s | 0.000us | 1 | 1 | 100.00 | |
| regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 450.230s | 0.000us | 1 | 1 | 100.00 | |
| ram_cfg | 1 | 1 | 100.00 | |||
| sram_ctrl_ram_cfg | 0.970s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_all | 1170.940s | 0.000us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sram_ctrl_alert_test | 0.900s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 3.010s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 3.010s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.720s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.790s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.680s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.670s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.720s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.790s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.680s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.670s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 2.470s | 0.000us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| sram_ctrl_sec_cm | 0.760s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_tl_intg_err | 2.020s | 0.000us | 1 | 1 | 100.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.760s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_intg_err | 2.020s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 450.230s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_readback_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 450.230s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.790s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 340.610s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_exec_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 340.610s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 340.610s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 6.350s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 1.120s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 2.470s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_mem_readback | 0 | 1 | 0.00 | |||
| sram_ctrl_readback_err | 0.750s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 21.020s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_addr_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 21.020s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 340.610s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.760s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_global_esc | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 6.350s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_key_local_esc | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.760s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_init_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.760s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 21.020s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.760s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 49.700s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) | ||||
| sram_ctrl_readback_err | 14135758547486665839510437396434734040508978963738022458807889004993354208667 | 98 |
UVM_ERROR @ 28602865 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x3e)
UVM_INFO @ 28602865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| sram_ctrl_stress_all_with_rand_reset | 48317748631634353426613449709216071552800901898429317752740411231693960852180 | 104 |
UVM_ERROR @ 3372880630 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3372880630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(curr_fwd | pend_req[d2h.d_source].pend)' | ||||
| sram_ctrl_sec_cm | 91065239299655253798997332561793758269831790781413715946829271104916896744820 | 101 |
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 3621939 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3621939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|