Simulation Results: uart

 
26/03/2026 16:02:32 DVSim: v1.16.0 sha: a1ef9e2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.16 %
  • code
  • 95.90 %
  • assert
  • 97.12 %
  • func
  • 44.45 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.45 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.130s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 0.000us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.660s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.120s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.820s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.690s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.660s 0.000us 1 1 100.00
uart_csr_aliasing 0.820s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 29.930s 0.000us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.130s 0.000us 1 1 100.00
uart_tx_rx 29.930s 0.000us 1 1 100.00
parity_error 2 2 100.00
uart_intr 27.230s 0.000us 1 1 100.00
uart_rx_parity_err 300.560s 0.000us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 29.930s 0.000us 1 1 100.00
uart_intr 27.230s 0.000us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 26.740s 0.000us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 10.670s 0.000us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 8.760s 0.000us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 27.230s 0.000us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 27.230s 0.000us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 27.230s 0.000us 1 1 100.00
perf 1 1 100.00
uart_perf 117.490s 0.000us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.350s 0.000us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.350s 0.000us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.480s 0.000us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.090s 0.000us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.520s 0.000us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 11.010s 0.000us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 339.720s 0.000us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 574.450s 0.000us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.610s 0.000us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.130s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.130s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 0.000us 1 1 100.00
uart_csr_rw 0.660s 0.000us 1 1 100.00
uart_csr_aliasing 0.820s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.730s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 0.000us 1 1 100.00
uart_csr_rw 0.660s 0.000us 1 1 100.00
uart_csr_aliasing 0.820s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.730s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.820s 0.000us 1 1 100.00
uart_tl_intg_err 1.130s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.130s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 64.590s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 55112653756569347509430504524959797245273007532262957157887570021208493080085 75
UVM_ERROR @ 2641802375 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0
UVM_ERROR @ 2641847830 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2642256925 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (245 [0xf5] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2642302380 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2642666020 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (245 [0xf5] vs 191 [0xbf]) reg name: uart_reg_block.rdata