Simulation Results: ac_range_check

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.88 %
  • code
  • 93.06 %
  • assert
  • 97.75 %
  • func
  • 57.84 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 33.000s 595.638us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 42.000s 4298.242us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 67.819us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 146.379us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 34.000s 17596.139us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 21.000s 3821.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 83.296us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 146.379us 1 1 100.00
ac_range_check_csr_aliasing 21.000s 3821.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 80.817us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 27.000s 1020.450us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 111.000s 12445.213us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 14.168us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 24.308us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 32.933us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 32.933us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 67.819us 1 1 100.00
ac_range_check_csr_rw 2.000s 146.379us 1 1 100.00
ac_range_check_csr_aliasing 21.000s 3821.625us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 560.399us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 67.819us 1 1 100.00
ac_range_check_csr_rw 2.000s 146.379us 1 1 100.00
ac_range_check_csr_aliasing 21.000s 3821.625us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 560.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 742.618us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 742.618us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 742.618us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 742.618us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 87.000s 4725.375us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_tl_intg_err 9.000s 7599.662us 1 1 100.00
ac_range_check_sec_cm 3.000s 17.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 235.000s 1880.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 28.000s 1126.054us 1 1 100.00