Simulation Results: aes/masked

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.87 %
  • code
  • 95.64 %
  • assert
  • 98.29 %
  • func
  • 66.67 %
  • block
  • 95.80 %
  • line
  • 97.49 %
  • branch
  • 89.60 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 115.094us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 60.544us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 204.369us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 160.728us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 191.667us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 228.414us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 63.407us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 160.728us 1 1 100.00
aes_csr_aliasing 2.000s 228.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 60.544us 1 1 100.00
aes_config_error 3.000s 577.527us 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 60.544us 1 1 100.00
aes_config_error 3.000s 577.527us 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 140.094us 1 1 100.00
aes_b2b 13.000s 1199.847us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 60.544us 1 1 100.00
aes_config_error 3.000s 577.527us 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
aes_alert_reset 4.000s 335.947us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 136.726us 1 1 100.00
aes_config_error 3.000s 577.527us 1 1 100.00
aes_alert_reset 4.000s 335.947us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 214.166us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 1740.458us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 9.000s 363.524us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 335.947us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 140.094us 1 1 100.00
aes_sideload 3.000s 153.951us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 201.993us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 64.000s 1208.732us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 116.316us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 90.431us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 84.993us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 84.993us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 204.369us 1 1 100.00
aes_csr_rw 2.000s 160.728us 1 1 100.00
aes_csr_aliasing 2.000s 228.414us 1 1 100.00
aes_same_csr_outstanding 2.000s 104.802us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 204.369us 1 1 100.00
aes_csr_rw 2.000s 160.728us 1 1 100.00
aes_csr_aliasing 2.000s 228.414us 1 1 100.00
aes_same_csr_outstanding 2.000s 104.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 74.923us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 100.824us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 100.824us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 100.824us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 100.824us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 202.527us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 184.723us 1 1 100.00
aes_sec_cm 5.000s 1592.190us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 184.723us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 335.947us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 100.824us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 100.824us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 60.544us 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
aes_alert_reset 4.000s 335.947us 1 1 100.00
aes_core_fi 48.000s 10020.027us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 3.000s 116.316us 1 1 100.00
aes_config_error 3.000s 577.527us 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
aes_core_fi 48.000s 10020.027us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 100.824us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 61.971us 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 140.094us 1 1 100.00
aes_sideload 3.000s 153.951us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 61.971us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 61.971us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 61.971us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 61.971us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 61.971us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 140.094us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 160.076us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
aes_ctr_fi 2.000s 79.321us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 160.076us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 160.076us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_ctr_fi 2.000s 79.321us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 160.076us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
aes_ctr_fi 2.000s 79.321us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 335.947us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
aes_ctr_fi 2.000s 79.321us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
aes_ctr_fi 2.000s 79.321us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_ctr_fi 2.000s 79.321us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_ghash_fi 2.000s 93.588us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 160.076us 1 1 100.00
aes_control_fi 2.000s 51.585us 1 1 100.00
aes_cipher_fi 2.000s 70.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 12.000s 1076.864us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 30638350952971076890145187989414428515964200067063440490576685144640287309430 142
UVM_FATAL @ 10020027370 ps: (aes_core_fi_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10020027370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 91965230636303708801192917165831129919486505556894704175702680638448771843922 378
UVM_FATAL @ 1076864084 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1076864084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---