Simulation Results: csrng

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.06 %
  • code
  • 92.47 %
  • assert
  • 93.23 %
  • func
  • 81.48 %
  • block
  • 97.18 %
  • line
  • 97.87 %
  • branch
  • 92.92 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 65.421us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 21.562us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 20.424us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 114.457us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 178.240us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 46.064us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 20.424us 1 1 100.00
csrng_csr_aliasing 4.000s 178.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 407.876us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 57.000s 3414.788us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 57.000s 3414.788us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 66.000s 4540.595us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 53.557us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 46.521us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 170.185us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 170.185us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 21.562us 1 1 100.00
csrng_csr_rw 2.000s 20.424us 1 1 100.00
csrng_csr_aliasing 4.000s 178.240us 1 1 100.00
csrng_same_csr_outstanding 2.000s 51.417us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 21.562us 1 1 100.00
csrng_csr_rw 2.000s 20.424us 1 1 100.00
csrng_csr_aliasing 4.000s 178.240us 1 1 100.00
csrng_same_csr_outstanding 2.000s 51.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 4.000s 224.547us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 20.424us 1 1 100.00
csrng_regwen 3.000s 12.112us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 407.876us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 66.000s 4540.595us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 407.876us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 66.000s 4540.595us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 407.876us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 224.547us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
csrng_sec_cm 3.000s 78.231us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 233.940us 1 1 100.00
csrng_err 2.000s 24.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 156.000s 7410.046us 1 1 100.00