Simulation Results: dma

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.38 %
  • code
  • 92.17 %
  • assert
  • 95.97 %
  • func
  • 62.00 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 1105.219us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 7.000s 326.663us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 252.961us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 18.508us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 18.125us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 5.000s 152.696us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 8.000s 468.512us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 3.000s 43.914us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 18.125us 1 1 100.00
dma_csr_aliasing 8.000s 468.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 61.000s 21221.951us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 116.000s 36053.636us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 670.000s 385944.672us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 670.000s 385944.672us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 116.000s 36053.636us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 198.000s 23416.118us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 670.000s 385944.672us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 5296.166us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 330.000s 149261.175us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 111.883us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 16.381us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 106.018us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 106.018us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 18.508us 1 1 100.00
dma_csr_rw 2.000s 18.125us 1 1 100.00
dma_csr_aliasing 8.000s 468.512us 1 1 100.00
dma_same_csr_outstanding 3.000s 87.082us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 18.508us 1 1 100.00
dma_csr_rw 2.000s 18.125us 1 1 100.00
dma_csr_aliasing 8.000s 468.512us 1 1 100.00
dma_same_csr_outstanding 3.000s 87.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 8.000s 131.334us 1 1 100.00
dma_generic_stress 198.000s 23416.118us 1 1 100.00
dma_handshake_stress 670.000s 385944.672us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 329.783us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 30.652us 1 1 100.00
dma_tl_intg_err 2.000s 120.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 51.000s 4752.099us 1 1 100.00
dma_longer_transfer 3.000s 135.105us 1 1 100.00
dma_stress_all_with_rand_reset 4.000s 113.434us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 81724495315139752501146669916225896812516112504376221518821919481094376497786 92
UVM_ERROR @ 113433919ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 113433919ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---