Simulation Results: edn/edn0

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.25 %
  • code
  • 85.81 %
  • assert
  • 96.96 %
  • func
  • 75.99 %
  • line
  • 98.32 %
  • branch
  • 94.42 %
  • cond
  • 85.95 %
  • toggle
  • 92.29 %
  • FSM
  • 58.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.110s 46.591us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 19.700us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.870s 14.967us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.330s 62.366us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.180s 38.768us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.490s 88.840us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.870s 14.967us 1 1 100.00
edn_csr_aliasing 1.180s 38.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.090s 37.658us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.090s 37.658us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.090s 37.658us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 29.614us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.210s 50.788us 1 1 100.00
errs 1 1 100.00
edn_err 1.040s 29.719us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 18.079us 1 1 100.00
edn_disable_auto_req_mode 1.020s 66.901us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.700s 70.339us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 33.012us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.990s 46.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.190s 168.678us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.190s 168.678us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.700us 1 1 100.00
edn_csr_rw 0.870s 14.967us 1 1 100.00
edn_csr_aliasing 1.180s 38.768us 1 1 100.00
edn_same_csr_outstanding 1.390s 156.026us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.700us 1 1 100.00
edn_csr_rw 0.870s 14.967us 1 1 100.00
edn_csr_aliasing 1.180s 38.768us 1 1 100.00
edn_same_csr_outstanding 1.390s 156.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.640s 188.758us 1 1 100.00
edn_sec_cm 6.200s 1096.128us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 28.760us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.210s 50.788us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.200s 1096.128us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.200s 1096.128us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.200s 1096.128us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.200s 1096.128us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.210s 50.788us 1 1 100.00
edn_sec_cm 6.200s 1096.128us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.210s 50.788us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.640s 188.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 73.460s 3913.563us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
edn_stress_all_with_rand_reset 45136124824520424306653332178465052227367697349784957630279416788333391661876 339
UVM_ERROR @ 3913562557 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3913562557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---