Simulation Results: edn/edn1

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.42 %
  • code
  • 82.28 %
  • assert
  • 97.14 %
  • func
  • 79.83 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 89.54 %
  • toggle
  • 87.42 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.040s 51.779us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.990s 19.884us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 30.380us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.360s 165.963us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.960s 53.308us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.270s 22.344us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 30.380us 1 1 100.00
edn_csr_aliasing 0.960s 53.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 61.856us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 61.856us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 61.856us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 27.153us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.080s 56.556us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 68.779us 1 1 100.00
disable 2 2 100.00
edn_disable 0.920s 13.905us 1 1 100.00
edn_disable_auto_req_mode 0.940s 66.590us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.010s 67.544us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 20.331us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 18.401us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.900s 126.149us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.900s 126.149us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.990s 19.884us 1 1 100.00
edn_csr_rw 0.810s 30.380us 1 1 100.00
edn_csr_aliasing 0.960s 53.308us 1 1 100.00
edn_same_csr_outstanding 1.040s 350.877us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.990s 19.884us 1 1 100.00
edn_csr_rw 0.810s 30.380us 1 1 100.00
edn_csr_aliasing 0.960s 53.308us 1 1 100.00
edn_same_csr_outstanding 1.040s 350.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.510s 54.745us 1 1 100.00
edn_sec_cm 2.130s 166.878us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 31.229us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.080s 56.556us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.130s 166.878us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.130s 166.878us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.130s 166.878us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.130s 166.878us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.080s 56.556us 1 1 100.00
edn_sec_cm 2.130s 166.878us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.080s 56.556us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.510s 54.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 31.800s 7633.344us 1 1 100.00