| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
50.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.260s | 625.581us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.100s | 42.942us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 0.870s | 59.496us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 0.890s | 33.639us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.720s | 58.310us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.700s | 15.365us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 2.170s | 78.003us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 2.170s | 169.218us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 0.920s | 29.818us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.700s | 15.365us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 2.170s | 169.218us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.210s | 188.145us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.160s | 55.843us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.770s | 15.379us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.720s | 143.401us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 1.670s | 85.047us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 1.670s | 92.891us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 16.890s | 932.655us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 4.040s | 299.365us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 0.800s | 182.165us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 0.670s | 26.573us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.690s | 37.160us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.670s | 24.291us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.010s | 50.623us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.010s | 50.623us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.700s | 15.365us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.050s | 42.771us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 2.170s | 169.218us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.720s | 58.310us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.700s | 15.365us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.050s | 42.771us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 2.170s | 169.218us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.720s | 58.310us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| gpio_sec_cm | 0.830s | 59.515us | 1 | 1 | 100.00 | |
| gpio_tl_intg_err | 1.480s | 96.454us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| gpio_tl_intg_err | 1.480s | 96.454us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.760s | 34.212us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 1.040s | 10.649us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.650s | 69.798us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| gpio_stress_all | 63261664705612135550818619439466120327011595855115248874098686845118676815883 | 76 |
UVM_ERROR @ 26572847 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 271132659 [0x102927f3])
UVM_INFO @ 26572847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) | ||||
| gpio_stress_all_with_rand_reset | 47971773469701345488910356139518138932162920492939263056235845364820279452097 | 85 |
UVM_FATAL @ 10649005 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 10649005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * | ||||
| gpio_tl_intg_err | 98685658363435618666288543279136141934680670470477490979496134151019397696116 | 231 |
UVM_ERROR @ 96453585 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: gpio_reg_block.inp_prd_cnt_val_3 reset value: 0x0
UVM_INFO @ 96453585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|