Simulation Results: hmac

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.82 %
  • code
  • 97.62 %
  • assert
  • 96.70 %
  • func
  • 42.14 %
  • line
  • 99.59 %
  • branch
  • 98.68 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.090s 1911.946us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.670s 22.198us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.810s 108.361us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.980s 1064.454us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.500s 1701.786us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.340s 54.644us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.810s 108.361us 1 1 100.00
hmac_csr_aliasing 5.500s 1701.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 46.710s 1210.525us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 24.510s 2483.862us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 179.220s 5543.543us 1 1 100.00
hmac_test_sha384_vectors 18.860s 950.023us 1 1 100.00
hmac_test_sha512_vectors 18.810s 844.057us 1 1 100.00
hmac_test_hmac256_vectors 5.240s 2857.035us 1 1 100.00
hmac_test_hmac384_vectors 8.250s 2163.674us 1 1 100.00
hmac_test_hmac512_vectors 6.980s 790.637us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 4.120s 838.276us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 341.050s 3254.288us 1 1 100.00
error 1 1 100.00
hmac_error 7.610s 1116.706us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 27.280s 14929.256us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.090s 1911.946us 1 1 100.00
hmac_long_msg 46.710s 1210.525us 1 1 100.00
hmac_back_pressure 24.510s 2483.862us 1 1 100.00
hmac_datapath_stress 341.050s 3254.288us 1 1 100.00
hmac_burst_wr 4.120s 838.276us 1 1 100.00
hmac_stress_all 0.620s 68.022us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.090s 1911.946us 1 1 100.00
hmac_long_msg 46.710s 1210.525us 1 1 100.00
hmac_back_pressure 24.510s 2483.862us 1 1 100.00
hmac_datapath_stress 341.050s 3254.288us 1 1 100.00
hmac_wipe_secret 27.280s 14929.256us 1 1 100.00
hmac_test_sha256_vectors 179.220s 5543.543us 1 1 100.00
hmac_test_sha384_vectors 18.860s 950.023us 1 1 100.00
hmac_test_sha512_vectors 18.810s 844.057us 1 1 100.00
hmac_test_hmac256_vectors 5.240s 2857.035us 1 1 100.00
hmac_test_hmac384_vectors 8.250s 2163.674us 1 1 100.00
hmac_test_hmac512_vectors 6.980s 790.637us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.090s 1911.946us 1 1 100.00
hmac_long_msg 46.710s 1210.525us 1 1 100.00
hmac_back_pressure 24.510s 2483.862us 1 1 100.00
hmac_datapath_stress 341.050s 3254.288us 1 1 100.00
hmac_burst_wr 4.120s 838.276us 1 1 100.00
hmac_error 7.610s 1116.706us 1 1 100.00
hmac_wipe_secret 27.280s 14929.256us 1 1 100.00
hmac_test_sha256_vectors 179.220s 5543.543us 1 1 100.00
hmac_test_sha384_vectors 18.860s 950.023us 1 1 100.00
hmac_test_sha512_vectors 18.810s 844.057us 1 1 100.00
hmac_test_hmac256_vectors 5.240s 2857.035us 1 1 100.00
hmac_test_hmac384_vectors 8.250s 2163.674us 1 1 100.00
hmac_test_hmac512_vectors 6.980s 790.637us 1 1 100.00
hmac_stress_all 0.620s 68.022us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 0.620s 68.022us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.580s 16.380us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 46.852us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.010s 38.180us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.010s 38.180us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.670s 22.198us 1 1 100.00
hmac_csr_rw 0.810s 108.361us 1 1 100.00
hmac_csr_aliasing 5.500s 1701.786us 1 1 100.00
hmac_same_csr_outstanding 1.780s 45.558us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.670s 22.198us 1 1 100.00
hmac_csr_rw 0.810s 108.361us 1 1 100.00
hmac_csr_aliasing 5.500s 1701.786us 1 1 100.00
hmac_same_csr_outstanding 1.780s 45.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.910s 1713.159us 1 1 100.00
hmac_tl_intg_err 1.470s 320.223us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.470s 320.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.090s 1911.946us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.180s 1117.822us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 20.780s 9907.012us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.010s 689.390us 1 1 100.00