Simulation Results: kmac/unmasked

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.50 %
  • code
  • 88.69 %
  • assert
  • 97.75 %
  • func
  • 91.05 %
  • line
  • 97.23 %
  • branch
  • 94.95 %
  • cond
  • 93.59 %
  • toggle
  • 99.83 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 46.300s 4245.992us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.170s 42.539us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.080s 51.932us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 5.760s 229.163us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.690s 565.772us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.460s 48.498us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.080s 51.932us 1 1 100.00
kmac_csr_aliasing 5.690s 565.772us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.700s 31.215us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.250s 27.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1122.620s 54659.953us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 39.020s 1457.514us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1158.030s 35590.094us 1 1 100.00
kmac_test_vectors_sha3_256 28.110s 1872.503us 1 1 100.00
kmac_test_vectors_sha3_384 847.660s 52911.218us 1 1 100.00
kmac_test_vectors_sha3_512 711.420s 120224.925us 1 1 100.00
kmac_test_vectors_shake_128 1875.120s 146588.578us 1 1 100.00
kmac_test_vectors_shake_256 1142.950s 67568.410us 1 1 100.00
kmac_test_vectors_kmac 2.540s 446.850us 1 1 100.00
kmac_test_vectors_kmac_xof 2.060s 94.559us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 72.750s 15517.778us 1 1 100.00
app 1 1 100.00
kmac_app 102.130s 8673.618us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 213.530s 49050.211us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 108.350s 98480.147us 1 1 100.00
error 1 1 100.00
kmac_error 158.780s 10411.395us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 3.680s 2783.238us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 45.800s 10016.783us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 19.020s 1995.055us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 10.410s 786.437us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 24.100s 3455.403us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.510s 37.222us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 990.360s 62776.344us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.920s 30.544us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.920s 214.401us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.080s 1365.153us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.080s 1365.153us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.170s 42.539us 1 1 100.00
kmac_csr_rw 1.080s 51.932us 1 1 100.00
kmac_csr_aliasing 5.690s 565.772us 1 1 100.00
kmac_same_csr_outstanding 2.310s 178.426us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.170s 42.539us 1 1 100.00
kmac_csr_rw 1.080s 51.932us 1 1 100.00
kmac_csr_aliasing 5.690s 565.772us 1 1 100.00
kmac_same_csr_outstanding 2.310s 178.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.630s 94.290us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.630s 94.290us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.630s 94.290us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.630s 94.290us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.130s 1043.757us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 3.860s 943.379us 1 1 100.00
kmac_sec_cm 19.580s 14354.095us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.860s 943.379us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.510s 37.222us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 46.300s 4245.992us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 72.750s 15517.778us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.630s 94.290us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 19.580s 14354.095us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 19.580s 14354.095us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 19.580s 14354.095us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 46.300s 4245.992us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.510s 37.222us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 19.580s 14354.095us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 74.120s 18154.593us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 46.300s 4245.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 113.830s 11860.740us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 79580968428197880805381322481897227946769908757506950878926764323285369950306 78
UVM_FATAL @ 10016783085 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2b0c7000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10016783085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---