Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.97 %
  • code
  • 85.00 %
  • assert
  • 95.99 %
  • func
  • 91.91 %
  • line
  • 97.69 %
  • branch
  • 96.13 %
  • cond
  • 79.75 %
  • toggle
  • 89.63 %
  • FSM
  • 61.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.460s 31.168us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 23.257us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.740s 15.065us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.490s 408.637us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 74.742us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.490s 21.399us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.740s 15.065us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 74.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.670s 72.941us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.850s 319.596us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.910s 13.770us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.470s 79.383us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 12.230s 1608.149us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_prog_failure 2.470s 79.383us 1 1 100.00
lc_ctrl_errors 12.230s 1608.149us 1 1 100.00
lc_ctrl_security_escalation 4.900s 740.384us 1 1 100.00
lc_ctrl_jtag_state_failure 27.020s 4469.296us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.250s 753.543us 1 1 100.00
lc_ctrl_jtag_errors 94.040s 23321.699us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 2.170s 92.932us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.250s 59.014us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.660s 3307.309us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.910s 1019.527us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.170s 29.936us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.860s 112.515us 1 1 100.00
lc_ctrl_jtag_alert_test 1.280s 262.475us 1 1 100.00
lc_ctrl_jtag_smoke 2.080s 1115.250us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.210s 11282.485us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.250s 753.543us 1 1 100.00
lc_ctrl_jtag_errors 94.040s 23321.699us 1 1 100.00
lc_ctrl_jtag_access 7.020s 1505.079us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.250s 1135.945us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.570s 2818.105us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.970s 14.321us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 350.920s 15895.542us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 21.173us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.630s 91.340us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.630s 91.340us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 23.257us 1 1 100.00
lc_ctrl_csr_rw 0.740s 15.065us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 74.742us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 21.849us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 23.257us 1 1 100.00
lc_ctrl_csr_rw 0.740s 15.065us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 74.742us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 21.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 2.250s 189.883us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.250s 189.883us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.850s 319.596us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.150s 592.782us 1 1 100.00
lc_ctrl_sec_cm 6.040s 463.859us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.900s 740.384us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.670s 72.941us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.210s 11282.485us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.310s 787.373us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.310s 787.373us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.920s 231.851us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.880s 1848.767us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.880s 1848.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.480s 190.226us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 98542984111588366883754076585125887785181510396791023662882049442400927372066 151
UVM_ERROR @ 190226152 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 190226152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---