Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.38 %
  • code
  • 84.97 %
  • assert
  • 95.99 %
  • func
  • 93.17 %
  • line
  • 97.71 %
  • branch
  • 96.01 %
  • cond
  • 79.79 %
  • toggle
  • 87.72 %
  • FSM
  • 63.64 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.680s 128.845us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.750s 15.045us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.960s 43.124us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.090s 71.287us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 32.234us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.230s 23.486us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.960s 43.124us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 32.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.600s 180.748us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.210s 645.344us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.810s 27.924us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.120s 447.507us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.020s 1521.076us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_prog_failure 2.120s 447.507us 1 1 100.00
lc_ctrl_errors 5.020s 1521.076us 1 1 100.00
lc_ctrl_security_escalation 4.590s 1161.292us 1 1 100.00
lc_ctrl_jtag_state_failure 17.960s 14130.627us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.490s 350.435us 1 1 100.00
lc_ctrl_jtag_errors 13.410s 1338.963us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 10.770s 1321.066us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.820s 606.218us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.490s 350.435us 1 1 100.00
lc_ctrl_jtag_errors 13.410s 1338.963us 1 1 100.00
lc_ctrl_jtag_access 4.210s 2722.925us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.750s 6433.055us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.270s 90.482us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.400s 83.138us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.170s 828.873us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.990s 477.749us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.120s 137.382us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.780s 1230.257us 1 1 100.00
lc_ctrl_jtag_alert_test 1.480s 228.805us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 13.150s 814.553us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.800s 22.652us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 64.530s 10654.251us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.070s 24.765us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.670s 49.049us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.670s 49.049us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 15.045us 1 1 100.00
lc_ctrl_csr_rw 0.960s 43.124us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 32.234us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 120.190us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 15.045us 1 1 100.00
lc_ctrl_csr_rw 0.960s 43.124us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 32.234us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 120.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
lc_ctrl_tl_intg_err 1.660s 997.184us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.660s 997.184us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.210s 645.344us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.360s 282.675us 1 1 100.00
lc_ctrl_sec_cm 6.030s 141.694us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.590s 1161.292us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.600s 180.748us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.820s 606.218us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.010s 238.807us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.010s 238.807us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.220s 1243.727us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.520s 551.561us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.520s 551.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 68.700s 13389.096us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
lc_ctrl_stress_all 24352800057858170191495671046131037053528711759528567031653274485795960887678 7340
UVM_ERROR @ 10654250557 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 10654250557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---