Simulation Results: otbn

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.29 %
  • code
  • 95.47 %
  • assert
  • 89.92 %
  • func
  • 97.46 %
  • block
  • 99.43 %
  • line
  • 99.59 %
  • branch
  • 92.84 %
  • toggle
  • 92.03 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 47.756us 1 1 100.00
single_binary 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 16.294us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 47.537us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 106.173us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 35.090us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 4.000s 43.663us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 47.537us 1 1 100.00
otbn_csr_aliasing 3.000s 35.090us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 98.000s 3530.651us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 40.000s 348.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 107.072us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 39.000s 469.508us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 101.000s 914.056us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 15.000s 55.599us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 5.000s 95.053us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 54.390us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 16.687us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 17.635us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 23.670us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 111.875us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 111.875us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 16.294us 1 1 100.00
otbn_csr_rw 4.000s 47.537us 1 1 100.00
otbn_csr_aliasing 3.000s 35.090us 1 1 100.00
otbn_same_csr_outstanding 3.000s 15.772us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 16.294us 1 1 100.00
otbn_csr_rw 4.000s 47.537us 1 1 100.00
otbn_csr_aliasing 3.000s 35.090us 1 1 100.00
otbn_same_csr_outstanding 3.000s 15.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 58.628us 1 1 100.00
otbn_dmem_err 6.000s 19.773us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 9.000s 59.477us 1 1 100.00
otbn_controller_ispr_rdata_err 5.000s 68.539us 1 1 100.00
otbn_mac_bignum_acc_err 6.000s 234.201us 1 1 100.00
otbn_urnd_err 6.000s 24.803us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 37.841us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 21.785us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 18.255us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
otbn_tl_intg_err 15.000s 250.661us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 13.000s 46.892us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 47.756us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 19.773us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 58.628us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 250.661us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 95.053us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 58.628us 1 1 100.00
otbn_dmem_err 6.000s 19.773us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 54.390us 1 1 100.00
otbn_illegal_mem_acc 4.000s 37.841us 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 58.628us 1 1 100.00
otbn_dmem_err 6.000s 19.773us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 54.390us 1 1 100.00
otbn_illegal_mem_acc 4.000s 37.841us 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 95.053us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 58.628us 1 1 100.00
otbn_dmem_err 6.000s 19.773us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 54.390us 1 1 100.00
otbn_illegal_mem_acc 4.000s 37.841us 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 44.663us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 12.181us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 29.000s 249.867us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 29.000s 249.867us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 25.800us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 61.086us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 16.000s 66.427us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 16.000s 66.427us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 36.424us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 101.000s 914.056us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 96.539us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 5.000s 56.347us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 95.000s 1943.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 53.000s 901.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 5.000s 52.651us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 50607058293354514795626939579246276221223098571460314737991530964325213225472 111
UVM_FATAL @ 46891753 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 46891753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---