Simulation Results: otp_ctrl

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.24 %
  • code
  • 72.65 %
  • assert
  • 90.48 %
  • func
  • 56.58 %
  • line
  • 87.36 %
  • branch
  • 82.74 %
  • cond
  • 85.58 %
  • toggle
  • 68.87 %
  • FSM
  • 38.70 %
Validation stages
V1
100.00%
V2
75.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.170s 56.103us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.470s 4155.090us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.910s 141.957us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.460s 46.501us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.940s 1432.341us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 9.010s 330.938us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.600s 1950.491us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.460s 46.501us 1 1 100.00
otp_ctrl_csr_aliasing 9.010s 330.938us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.510s 149.863us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.670s 81.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 126.160s 9929.826us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.960s 2612.282us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 15.690s 1967.242us 1 1 100.00
otp_ctrl_check_fail 2.410s 319.345us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.620s 562.845us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 28.320s 11580.642us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 11.520s 5029.794us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 16.810s 858.007us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 17.750s 2070.118us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.980s 291.932us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 8.470s 1599.223us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 67.900s 22244.774us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.520s 62.105us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.060s 150.082us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.840s 90.997us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.840s 90.997us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.910s 141.957us 1 1 100.00
otp_ctrl_csr_rw 2.460s 46.501us 1 1 100.00
otp_ctrl_csr_aliasing 9.010s 330.938us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.800s 72.424us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.910s 141.957us 1 1 100.00
otp_ctrl_csr_rw 2.460s 46.501us 1 1 100.00
otp_ctrl_csr_aliasing 9.010s 330.938us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.800s 72.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_tl_intg_err 23.950s 5570.477us 1 1 100.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 23.950s 5570.477us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.470s 4155.090us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.470s 4155.090us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
otp_ctrl_macro_errs 3.980s 291.932us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
otp_ctrl_macro_errs 3.980s 291.932us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.210s 469.511us 1 1 100.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.960s 2612.282us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 2.410s 319.345us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 28.320s 11580.642us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 28.320s 11580.642us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 28.320s 11580.642us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 28.320s 11580.642us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 28.320s 11580.642us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.470s 4155.090us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 28.320s 11580.642us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.470s 4155.090us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 143.780s 76647.608us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.620s 562.845us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.470s 4155.090us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.470s 4155.090us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.980s 291.932us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 64.680s 22350.517us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.540s 65.393us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 73805403298214129511259684946637303527350662631857859248332137164960768644181 120719
UVM_ERROR @ 9929826311 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_partition_walk_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 16080 [0x3ed0]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 9929826311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 79861099421345943308136727600920943513732263244079510146771037861767112728404 89
UVM_ERROR @ 22350516532 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 22350516532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 96213240356096144092374168978760233231366915076460492629808369338439653648910 90
UVM_ERROR @ 22244773943 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 22244773943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_dai_lock 79859860824207786499611368671407945823131962774239572516956583990991136279499 10216
UVM_ERROR @ 11580642319 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 11580642319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 82068882850635547441426062671746604671888536478294428714630217858867036839311 1166
UVM_ERROR @ 291932470 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1022708151 [0x3cf549b7] vs 1022708663 [0x3cf54bb7]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 291932470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_test_access 64219290216900632797802091478233053563424424066518579717871353809635558801378 7271
UVM_ERROR @ 1599223434 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1599223434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 114645052636956675335222294717795068280709862390903812104724463974156099532754 98
UVM_ERROR @ 65392967 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 65392967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 97590941968298152004868707447573803320011160771264385066047578356384161576597 1152
UVM_ERROR @ 76647607686 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 76647607686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---