Simulation Results: rom_ctrl/32kb

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.81 %
  • code
  • 96.72 %
  • assert
  • 96.80 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.22 %
  • toggle
  • 100.00 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.490s 591.750us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.650s 839.078us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.660s 297.535us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.920s 293.689us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.650s 174.271us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.680s 753.479us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.660s 297.535us 1 1 100.00
rom_ctrl_csr_aliasing 4.650s 174.271us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.350s 135.739us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.930s 371.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.730s 139.560us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.320s 987.565us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.650s 1002.036us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.390s 126.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.510s 385.922us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.510s 385.922us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.650s 839.078us 1 1 100.00
rom_ctrl_csr_rw 3.660s 297.535us 1 1 100.00
rom_ctrl_csr_aliasing 4.650s 174.271us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.590s 534.205us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.650s 839.078us 1 1 100.00
rom_ctrl_csr_rw 3.660s 297.535us 1 1 100.00
rom_ctrl_csr_aliasing 4.650s 174.271us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.590s 534.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.750s 1170.616us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 41.360s 1317.556us 1 1 100.00
rom_ctrl_sec_cm 190.820s 946.875us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 190.820s 946.875us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 190.820s 946.875us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 190.820s 946.875us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 190.820s 946.875us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.490s 591.750us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.490s 591.750us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.490s 591.750us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.360s 1317.556us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
rom_ctrl_kmac_err_chk 7.650s 1002.036us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 38.690s 1154.537us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.750s 1170.616us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 190.820s 946.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 58.820s 9618.720us 1 1 100.00