Simulation Results: rom_ctrl/64kb

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.24 %
  • code
  • 97.55 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 96.73 %
  • toggle
  • 99.69 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.920s 572.485us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.920s 381.996us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.520s 3330.245us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.490s 302.442us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.840s 544.655us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.320s 213.553us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.520s 3330.245us 1 1 100.00
rom_ctrl_csr_aliasing 6.840s 544.655us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.220s 303.814us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.720s 379.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.880s 764.171us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 27.840s 760.185us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.070s 2108.285us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 8.950s 2232.576us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.510s 1070.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.510s 1070.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.920s 381.996us 1 1 100.00
rom_ctrl_csr_rw 5.520s 3330.245us 1 1 100.00
rom_ctrl_csr_aliasing 6.840s 544.655us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.040s 2005.598us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.920s 381.996us 1 1 100.00
rom_ctrl_csr_rw 5.520s 3330.245us 1 1 100.00
rom_ctrl_csr_aliasing 6.840s 544.655us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.040s 2005.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.620s 5678.513us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 452.280s 2471.291us 1 1 100.00
rom_ctrl_tl_intg_err 51.830s 287.313us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 452.280s 2471.291us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 452.280s 2471.291us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 452.280s 2471.291us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 452.280s 2471.291us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.920s 572.485us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.920s 572.485us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.920s 572.485us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 51.830s 287.313us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
rom_ctrl_kmac_err_chk 14.070s 2108.285us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 87.690s 1656.641us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.620s 5678.513us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 452.280s 2471.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 146.970s 4968.347us 1 1 100.00