Simulation Results: rstmgr

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.54 %
  • code
  • 99.30 %
  • assert
  • 97.25 %
  • func
  • 96.08 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.170s 67.339us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.920s 65.875us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.820s 37.032us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.560s 143.308us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.970s 43.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.960s 66.709us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.820s 37.032us 1 1 100.00
rstmgr_csr_aliasing 0.970s 43.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.880s 63.199us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.880s 40.463us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.880s 64.106us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.330s 661.935us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.330s 661.935us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.330s 661.935us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.330s 661.935us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 28.640s 4539.007us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.850s 38.383us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.310s 75.821us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.310s 75.821us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 65.875us 1 1 100.00
rstmgr_csr_rw 0.820s 37.032us 1 1 100.00
rstmgr_csr_aliasing 0.970s 43.577us 1 1 100.00
rstmgr_same_csr_outstanding 1.060s 66.846us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 65.875us 1 1 100.00
rstmgr_csr_rw 0.820s 37.032us 1 1 100.00
rstmgr_csr_aliasing 0.970s 43.577us 1 1 100.00
rstmgr_same_csr_outstanding 1.060s 66.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 29.330s 6933.063us 1 1 100.00
rstmgr_tl_intg_err 2.310s 341.141us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 29.330s 6933.063us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 29.330s 6933.063us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.310s 341.141us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.950s 56.554us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.620s 471.561us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.880s 292.948us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 29.330s 6933.063us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 37.032us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 37.032us 1 1 100.00