Simulation Results: rv_timer

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.47 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.700s 294.031us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.680s 14.978us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.530s 44.363us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.260s 332.650us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.720s 24.033us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.700s 112.728us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.530s 44.363us 1 1 100.00
rv_timer_csr_aliasing 0.720s 24.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.590s 172.907us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.570s 69.385us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 60.700s 111653.292us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 60.700s 111653.292us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.160s 7552.952us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 47.153us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 39.637us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 148.482us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 148.482us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 14.978us 1 1 100.00
rv_timer_csr_rw 0.530s 44.363us 1 1 100.00
rv_timer_csr_aliasing 0.720s 24.033us 1 1 100.00
rv_timer_same_csr_outstanding 0.790s 112.423us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 14.978us 1 1 100.00
rv_timer_csr_rw 0.530s 44.363us 1 1 100.00
rv_timer_csr_aliasing 0.720s 24.033us 1 1 100.00
rv_timer_same_csr_outstanding 0.790s 112.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 40.710us 1 1 100.00
rv_timer_tl_intg_err 0.950s 83.448us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.950s 83.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.590s 237.167us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.590s 88.774us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 32.690s 29954.246us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 60629714896789050583155086822287560719838223083193395218018739940824566454670 76
UVM_FATAL @ 237166722 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd86cf504) == 0x1
UVM_INFO @ 237166722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 45008540080261154396338858666638683988778923900428342924453073052370659246160 75
UVM_FATAL @ 172907313 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8c06b304) == 0x1
UVM_INFO @ 172907313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 40361158550717416745368944993579417447140471673835815125515870832550281624424 75
UVM_ERROR @ 88774144 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 88774144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---