Simulation Results

Simulation Results: spi_device/1r1w

30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.48 %

code
93.20 %

assert
94.64 %

func
62.60 %

line
98.99 %

branch
98.14 %

cond
95.96 %

toggle
83.54 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	53.560s	14485.604us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	1.190s	24.146us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.610s	310.393us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	18.340s	3606.428us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	14.930s	1872.569us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	1.330s	96.403us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.610s	310.393us	1	1	100.00
	spi_device_csr_aliasing	14.930s	1872.569us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.630s	17.114us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.600s	207.948us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.780s	52.396us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.720s	2.774us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.790s	3.450us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	0.910s	109.234us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	0.910s	109.234us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	6.820s	8598.064us	1	1	100.00
	spi_device_tpm_sts_read	0.650s	164.635us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	19.770s	4928.400us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	2.570s	1358.971us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	2.910s	941.719us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	2.910s	941.719us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	2.690s	297.830us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	2.690s	297.830us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	2.690s	297.830us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	2.690s	297.830us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	2.690s	297.830us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	5.020s	866.848us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	20.120s	2417.889us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	20.120s	2417.889us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	20.120s	2417.889us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	6.490s	797.096us	1	1	100.00
	spi_device_read_buffer_direct	2.750s	554.684us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	20.120s	2417.889us	1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	59.000s	21937.362us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	2.190s	105.449us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	2.190s	105.449us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	53.560s	14485.604us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	85.080s	17418.567us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	17.780s	3671.315us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.990s	23.228us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.720s	14.081us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	3.510s	360.931us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	3.510s	360.931us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	1.190s	24.146us	1	1	100.00
	spi_device_csr_rw	1.610s	310.393us	1	1	100.00
	spi_device_csr_aliasing	14.930s	1872.569us	1	1	100.00
	spi_device_same_csr_outstanding	1.510s	51.903us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	1.190s	24.146us	1	1	100.00
	spi_device_csr_rw	1.610s	310.393us	1	1	100.00
	spi_device_csr_aliasing	14.930s	1872.569us	1	1	100.00
	spi_device_same_csr_outstanding	1.510s	51.903us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	8.150s	1177.221us	1	1	100.00
	spi_device_sec_cm	1.070s	98.552us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	8.150s	1177.221us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	6.170s	854.338us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	60959102309515087661905008652069957022811947152624437208070508920660136678425	76	UVM_ERROR @ 2406969 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[66]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 2406969 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 2406969 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[962]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	92098933196894046150247396913220982391206190649249460727253470197843897110656	76	UVM_ERROR @ 1246985 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x54f4f0 [10101001111010011110000] vs 0x0 [0]) UVM_ERROR @ 1308985 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9f5e7a [100111110101111001111010] vs 0x0 [0]) UVM_ERROR @ 1407985 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4ea7fc [10011101010011111111100] vs 0x0 [0]) UVM_ERROR @ 1502985 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x908096 [100100001000000010010110] vs 0x0 [0]) UVM_ERROR @ 1539985 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfb7fd2 [111110110111111111010010] vs 0x0 [0])