Simulation Results: sram_ctrl/main

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.38 %
  • code
  • 85.76 %
  • assert
  • 95.41 %
  • func
  • 89.98 %
  • line
  • 96.51 %
  • branch
  • 93.56 %
  • cond
  • 90.94 %
  • toggle
  • 90.65 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.530s 1687.598us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.740s 20.982us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.710s 21.171us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.180s 24.849us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.790s 36.103us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.210s 1641.556us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.710s 21.171us 1 1 100.00
sram_ctrl_csr_aliasing 0.790s 36.103us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 88.890s 1997.965us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 111.070s 18209.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 109.150s 2986.938us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 241.990s 5133.787us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 387.650s 33792.038us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 584.930s 12987.844us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.830s 5254.083us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 384.140s 8730.416us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.980s 2604.817us 1 1 100.00
sram_ctrl_partial_access_b2b 163.520s 9502.397us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 47.840s 802.937us 1 1 100.00
sram_ctrl_throughput_w_partial_write 24.750s 3110.151us 1 1 100.00
sram_ctrl_throughput_w_readback 30.450s 3849.561us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 193.020s 3253.786us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.150s 1206.986us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 4573.930s 463909.675us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.830s 36.486us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.390s 273.745us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.390s 273.745us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 20.982us 1 1 100.00
sram_ctrl_csr_rw 0.710s 21.171us 1 1 100.00
sram_ctrl_csr_aliasing 0.790s 36.103us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.670s 37.138us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 20.982us 1 1 100.00
sram_ctrl_csr_rw 0.710s 21.171us 1 1 100.00
sram_ctrl_csr_aliasing 0.790s 36.103us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.670s 37.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.430s 21686.929us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.730s 3.990us 0 1 0.00
sram_ctrl_tl_intg_err 1.880s 211.331us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.730s 3.990us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.880s 211.331us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 193.020s 3253.786us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 193.020s 3253.786us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.710s 21.171us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 384.140s 8730.416us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 384.140s 8730.416us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 384.140s 8730.416us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.830s 5254.083us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3.880s 2635.133us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.430s 21686.929us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.930s 676.421us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.530s 1687.598us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.530s 1687.598us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 384.140s 8730.416us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.730s 3.990us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.830s 5254.083us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.730s 3.990us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.730s 3.990us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.530s 1687.598us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.730s 3.990us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.940s 315.428us 1 1 100.00

Error Messages

   Test seed line log context
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 98356862569882437508322121067969598843986677918686649771460093406983525885057 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2635133253 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2635133253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 72900979333814173172316562762159908596699765205027491450247386925124877832784 99
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 3989595 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 3989595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---