Simulation Results: sram_ctrl/ret

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.76 %
  • code
  • 90.33 %
  • assert
  • 95.23 %
  • func
  • 95.73 %
  • line
  • 97.68 %
  • branch
  • 95.71 %
  • cond
  • 91.43 %
  • toggle
  • 90.66 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 12.930s 3047.079us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.770s 23.659us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.740s 22.528us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.300s 32.203us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 25.338us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 222.318us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.740s 22.528us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 25.338us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.490s 607.739us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.980s 290.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 127.700s 16044.088us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 288.020s 4036.596us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 49.150s 4488.106us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 845.570s 67071.356us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.700s 1065.931us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 69.640s 247.196us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 12.950s 310.751us 1 1 100.00
sram_ctrl_partial_access_b2b 307.310s 18391.337us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 30.300s 111.044us 1 1 100.00
sram_ctrl_throughput_w_partial_write 19.810s 109.843us 1 1 100.00
sram_ctrl_throughput_w_readback 58.370s 588.036us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 387.390s 2672.982us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.930s 78.616us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1045.650s 12966.597us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.760s 84.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.180s 77.914us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.180s 77.914us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.770s 23.659us 1 1 100.00
sram_ctrl_csr_rw 0.740s 22.528us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 25.338us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 46.925us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.770s 23.659us 1 1 100.00
sram_ctrl_csr_rw 0.740s 22.528us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 25.338us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 46.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.980s 559.436us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.730s 6.869us 0 1 0.00
sram_ctrl_tl_intg_err 2.070s 701.984us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.730s 6.869us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.070s 701.984us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 387.390s 2672.982us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 387.390s 2672.982us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.740s 22.528us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 69.640s 247.196us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 69.640s 247.196us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 69.640s 247.196us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.700s 1065.931us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.120s 480.748us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.980s 559.436us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.890s 32.695us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 12.930s 3047.079us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 12.930s 3047.079us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 69.640s 247.196us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.730s 6.869us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.700s 1065.931us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.730s 6.869us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.730s 6.869us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 12.930s 3047.079us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.730s 6.869us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 77.100s 899.625us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 74100790556777024266188857555467926502684221628932796316960092228679458843602 100
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 6868855 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6868855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---