Simulation Results: ac_range_check

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.44 %
  • code
  • 93.06 %
  • assert
  • 75.43 %
  • func
  • 57.84 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 21.000s 795.589us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 31.000s 1467.778us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 237.745us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 42.809us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 24.000s 1974.841us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1051.729us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 56.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 42.809us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1051.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 92.096us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 21.000s 480.262us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 65.000s 15222.563us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 14.844us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 40.053us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 69.434us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 69.434us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 237.745us 1 1 100.00
ac_range_check_csr_rw 3.000s 42.809us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1051.729us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 193.433us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 237.745us 1 1 100.00
ac_range_check_csr_rw 3.000s 42.809us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1051.729us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 193.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 791.369us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 791.369us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 791.369us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 791.369us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 61.000s 5863.464us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 35.098us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 1258.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 157.000s 3813.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 19.000s 375.388us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_stress_all 57585520934341359961375901616972148424333507488613886138769029419972847885617 8912
UVM_ERROR @ 15222562672 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 15222562672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---