Simulation Results: aes/unmasked

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.03 %
  • code
  • 90.91 %
  • assert
  • 97.75 %
  • func
  • 69.44 %
  • block
  • 91.00 %
  • line
  • 93.45 %
  • branch
  • 83.54 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 163.846us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 90.345us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 60.934us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 64.531us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 203.433us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 337.944us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 75.322us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 64.531us 1 1 100.00
aes_csr_aliasing 2.000s 337.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 90.345us 1 1 100.00
aes_config_error 3.000s 148.878us 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 90.345us 1 1 100.00
aes_config_error 3.000s 148.878us 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 206.328us 1 1 100.00
aes_b2b 3.000s 175.533us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 90.345us 1 1 100.00
aes_config_error 3.000s 148.878us 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
aes_alert_reset 3.000s 258.108us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 91.382us 1 1 100.00
aes_config_error 3.000s 148.878us 1 1 100.00
aes_alert_reset 3.000s 258.108us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 107.707us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 174.130us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 3.000s 110.630us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 258.108us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 206.328us 1 1 100.00
aes_sideload 2.000s 72.935us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 139.306us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 9.000s 513.471us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 110.541us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 64.185us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 1198.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 1198.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 60.934us 1 1 100.00
aes_csr_rw 2.000s 64.531us 1 1 100.00
aes_csr_aliasing 2.000s 337.944us 1 1 100.00
aes_same_csr_outstanding 2.000s 154.346us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 60.934us 1 1 100.00
aes_csr_rw 2.000s 64.531us 1 1 100.00
aes_csr_aliasing 2.000s 337.944us 1 1 100.00
aes_same_csr_outstanding 2.000s 154.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 125.270us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 5.000s 891.156us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 5.000s 891.156us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 5.000s 891.156us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 5.000s 891.156us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 187.793us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 130.403us 1 1 100.00
aes_sec_cm 4.000s 2332.461us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 130.403us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 258.108us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 5.000s 891.156us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 5.000s 891.156us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 90.345us 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
aes_alert_reset 3.000s 258.108us 1 1 100.00
aes_core_fi 25.000s 10023.944us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 2.000s 110.541us 1 1 100.00
aes_config_error 3.000s 148.878us 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
aes_core_fi 25.000s 10023.944us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 5.000s 891.156us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 90.850us 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 206.328us 1 1 100.00
aes_sideload 2.000s 72.935us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.850us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.850us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 90.850us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 90.850us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 90.850us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 206.328us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 71.598us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
aes_ctr_fi 2.000s 49.753us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 71.598us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 71.598us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_ctr_fi 2.000s 49.753us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 71.598us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
aes_ctr_fi 2.000s 49.753us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 258.108us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
aes_ctr_fi 2.000s 49.753us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
aes_ctr_fi 2.000s 49.753us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_ctr_fi 2.000s 49.753us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_ghash_fi 1.000s 50.049us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 2.000s 71.598us 1 1 100.00
aes_control_fi 2.000s 51.655us 1 1 100.00
aes_cipher_fi 2.000s 49.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 13.000s 1243.261us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 50577634014215865295306782368930188236647105898876085460705259964070153909238 145
UVM_FATAL @ 10023944032 ps: (aes_core_fi_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10023944032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 11770706154729657930066701340046636431379767428634089035741184587382111504185 1056
UVM_ERROR @ 1243261047 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1243261047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---