Simulation Results: alert_handler

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.27 %
  • code
  • 85.93 %
  • assert
  • 96.84 %
  • func
  • 55.05 %
  • block
  • 98.12 %
  • line
  • 99.37 %
  • branch
  • 96.36 %
  • toggle
  • 80.61 %
  • FSM
  • 67.37 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 71.000s 3802.331us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 17.000s 134.353us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.000s 38.784us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 745.000s 9776.795us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 142.000s 7273.525us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 11.000s 291.756us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.000s 38.784us 1 1 100.00
alert_handler_csr_aliasing 142.000s 7273.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 42.000s 310.156us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 31.000s 344.423us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2034.000s 233877.734us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 92.000s 1192.947us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 71.000s 3802.331us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 29.000s 1112.541us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 27.000s 689.446us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 326.000s 27371.723us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 2426.000s 419264.869us 1 1 100.00
alert_handler_lpg_stub_clk 1599.000s 10791.410us 1 1 100.00
stress_all 0 1 0.00
alert_handler_stress_all 22.000s 123.920us 0 1 0.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 36.000s 762.215us 1 1 100.00
alert_handler_alert_accum_saturation 0 1 0.00
alert_handler_alert_accum_saturation 3.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
alert_handler_intr_test 4.000s 19.466us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 24.000s 126.839us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 24.000s 126.839us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 17.000s 134.353us 1 1 100.00
alert_handler_csr_rw 7.000s 38.784us 1 1 100.00
alert_handler_csr_aliasing 142.000s 7273.525us 1 1 100.00
alert_handler_same_csr_outstanding 31.000s 5079.310us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 17.000s 134.353us 1 1 100.00
alert_handler_csr_rw 7.000s 38.784us 1 1 100.00
alert_handler_csr_aliasing 142.000s 7273.525us 1 1 100.00
alert_handler_same_csr_outstanding 31.000s 5079.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 380.000s 18465.410us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 380.000s 18465.410us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 380.000s 18465.410us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 380.000s 18465.410us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 804.000s 10364.629us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
alert_handler_tl_intg_err 6.000s 66.983us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 6.000s 66.983us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 380.000s 18465.410us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 71.000s 3802.331us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 71.000s 3802.331us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 71.000s 3802.331us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 71.000s 3802.331us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 92.000s 1192.947us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2426.000s 419264.869us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 92.000s 1192.947us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2034.000s 233877.734us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2034.000s 233877.734us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 11.000s 610.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 50.000s 615.265us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:488) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state
alert_handler_stress_all 42306569975694465998819852991853574614789753559394780269774812747209748965164 96
UVM_ERROR @ 123920107 ps: (alert_handler_scoreboard.sv:488) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 4 [0x4]) reg name: alert_handler_reg_block.classd_state
UVM_INFO @ 123920107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
alert_handler_alert_accum_saturation 35831894052515903570363547596811897128860806931945288910172046438191693153079 88
UVM_ERROR @ 0 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 0 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 94107931959180477815884228096163902406217240308418819102428539051534341897919 104
UVM_ERROR @ 615264745 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 615264745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---