| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| clkmgr_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 0 | 1 | 0.00 | |||
| clkmgr_peri | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| trans_enables | 0 | 1 | 0.00 | |||
| clkmgr_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clk_status | 0 | 1 | 0.00 | |||
| clkmgr_clk_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jitter | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_timeout | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_overflow | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| clkmgr_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| clkmgr_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timeout_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_shadow | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_idle_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_jitter_config_mubi | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 0 | 1 | 0.00 | |||
| clkmgr_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_*/seq_lib/clkmgr_regwen_vseq.sv,*|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes. | ||||
| default | None | 1003 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| cover_reg_top | None | 1003 |
xmvlog: *E,ENUMERR (src/lowrisc_darjeeling_dv_clkmgr_env_0.1/seq_lib/clkmgr_regwen_vseq.sv,21|52): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
package worklib.clkmgr_env_pkg:sv
errors: 1, warnings: 2
file: src/lowrisc_darjeeling_dv_clkmgr_env_0.1/clkmgr_if.sv
import clkmgr_env_pkg::*;
|
|
| Job killed most likely because its dependent job failed. | ||||
| clkmgr_smoke | 28810680304516985771443538121488178668419720731072079972739132089133986499804 | None | ||
| clkmgr_frequency | 54678947063877623473260713364209274673935001620220821545979055980334087145994 | None | ||
| clkmgr_frequency_timeout | 17087709466157139531227906776055663826691193812253726859481230118191681223423 | None | ||
| clkmgr_peri | 93167084079049295123209421225112473031655389848475347201938816623800545423366 | None | ||
| clkmgr_trans | 97789274346386154905519963740212788785709522824155399705931851865197167785033 | None | ||
| clkmgr_clk_status | 72926216272966700798172933668886679215284005190973335836608130502629853035267 | None | ||
| clkmgr_idle_intersig_mubi | 19610248115626332576607281802208408962355142301723007784291227498313584382908 | None | ||
| clkmgr_regwen | 112702469147838591213533255142391297427900314418299367419761871052366279665485 | None | ||
| clkmgr_sec_cm | 97794547063549859799252538164436098672213252581512750020649416196438479928369 | None | ||
| clkmgr_stress_all_with_rand_reset | 60197995908678632602764919130268884043209813428911238444969893356968680178563 | None | ||
| clkmgr_stress_all | 70863613475941291078911870676166594791745391817858505772791865486890939254931 | None | ||
| clkmgr_alert_test | 94550883851017081209943755541063723991842119329993019848396545463716827080212 | None | ||
| clkmgr_shadow_reg_errors | 16656189874315343250881168801022867853530069621341072519461396564053422248243 | None | ||
| clkmgr_shadow_reg_errors_with_csr_rw | 111913791084491608766435125498546891364754118696078148236570598961613470024350 | None | ||
| clkmgr_tl_errors | 4794678069169753952654180132511760670847281672084458884824918806371482936376 | None | ||
| clkmgr_tl_intg_err | 10710530113720782595728464983629002161958366330946358460780119794765647351572 | None | ||
| clkmgr_csr_hw_reset | 7511861653300577381868308221415987173477647330426848301195540854911425044223 | None | ||
| clkmgr_csr_rw | 18076899553730329544603048332597680094513863001718431621139339506776672350063 | None | ||
| clkmgr_csr_bit_bash | 42609604668085583913554862490147262533199511296452730759229033779285542998850 | None | ||
| clkmgr_csr_aliasing | 10036313772375272541218928922626493196715986190362488780745341084501357636461 | None | ||
| clkmgr_same_csr_outstanding | 114837916432699096353640176337113002469032280300367870284112027203976094339755 | None | ||
| clkmgr_csr_mem_rw_with_rand_reset | 70111394619046279138012242089499627142870579630695648519587636797448331780693 | None | ||
| clkmgr | None | None | ||
| clkmgr | None | None | ||