Simulation Results: dma

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.14 %
  • code
  • 92.20 %
  • assert
  • 95.87 %
  • func
  • 64.36 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 343.698us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 449.264us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 295.872us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 60.573us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 52.018us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 291.968us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 332.143us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 30.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 52.018us 1 1 100.00
dma_csr_aliasing 3.000s 332.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 84.000s 4889.586us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 340.000s 33507.017us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 514.000s 203416.431us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 514.000s 203416.431us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 340.000s 33507.017us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 213.000s 82015.401us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 514.000s 203416.431us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 3712.296us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 271.000s 42427.446us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 38.552us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 29.017us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 53.188us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 53.188us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 60.573us 1 1 100.00
dma_csr_rw 2.000s 52.018us 1 1 100.00
dma_csr_aliasing 3.000s 332.143us 1 1 100.00
dma_same_csr_outstanding 2.000s 177.046us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 60.573us 1 1 100.00
dma_csr_rw 2.000s 52.018us 1 1 100.00
dma_csr_aliasing 3.000s 332.143us 1 1 100.00
dma_same_csr_outstanding 2.000s 177.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 10.000s 212.845us 1 1 100.00
dma_generic_stress 213.000s 82015.401us 1 1 100.00
dma_handshake_stress 514.000s 203416.431us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 1134.825us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 165.178us 1 1 100.00
dma_sec_cm 1.000s 21.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 87.000s 5071.848us 1 1 100.00
dma_longer_transfer 9.000s 612.811us 1 1 100.00
dma_stress_all_with_rand_reset 15.000s 1930.104us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 22751389676985421239125120145977529606614491485173726566681526664193400815846 124
UVM_ERROR @ 1930104390ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1930104390ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---