Simulation Results: edn/edn0

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 78.79 %
  • code
  • 90.87 %
  • assert
  • 96.68 %
  • func
  • 48.81 %
  • block
  • 95.99 %
  • line
  • 97.76 %
  • branch
  • 91.39 %
  • toggle
  • 79.77 %
  • FSM
  • 94.57 %
Validation stages
V1
100.00%
V2
85.71%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 17.309us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 19.605us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 12.840us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 353.777us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 17.906us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 28.195us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 12.840us 1 1 100.00
edn_csr_aliasing 1.000s 17.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 96.017us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 96.017us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 96.017us 1 1 100.00
interrupts 0 1 0.00
edn_intr 1.000s 8.832us 0 1 0.00
alerts 1 1 100.00
edn_alert 2.000s 27.422us 1 1 100.00
errs 0 1 0.00
edn_err 1.000s 1.890us 0 1 0.00
disable 2 2 100.00
edn_disable 1.000s 24.058us 1 1 100.00
edn_disable_auto_req_mode 1.000s 260.700us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.000s 257.078us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 21.121us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 29.134us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 100.266us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 100.266us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 19.605us 1 1 100.00
edn_csr_rw 1.000s 12.840us 1 1 100.00
edn_csr_aliasing 1.000s 17.906us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.942us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 19.605us 1 1 100.00
edn_csr_rw 1.000s 12.840us 1 1 100.00
edn_csr_aliasing 1.000s 17.906us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 484.954us 1 1 100.00
edn_tl_intg_err 2.000s 159.157us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 19.094us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 27.422us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 484.954us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 484.954us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 484.954us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 484.954us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 27.422us 1 1 100.00
edn_sec_cm 4.000s 484.954us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 27.422us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 159.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.000s 10873.732us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_*/rtl/prim_count.sv,300): Assertion CntErrReported_A has failed (* cycles, starting * PS)
edn_intr 93847758024945703448676066209900266338706625127988082919190469629827415873151 128
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 8832204 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 8790537 PS)
UVM_ERROR @ 8832204 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
UVM_INFO @ 8832204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_err 26329956158500836659624002203373587818318475623050249373393996924149045082667 147
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 1890365 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 1880365 PS)
UVM_ERROR @ 1890365 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
UVM_INFO @ 1890365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---