| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status *), exiting. | ||||
| default | None | 1077 |
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting.
TOOL: xrun(64) 24.03-s007: Exiting on Mar 31, 2026 at 16:10:04 UTC (total: 00:00:11)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| cover_reg_top | None | 1061 |
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting.
TOOL: xrun(64) 24.03-s007: Exiting on Mar 31, 2026 at 16:10:05 UTC (total: 00:00:12)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 43714853463952375684167248474521589326824634267782169052811389576616776996151 | None | ||
| edn_regwen | 15198670345070607633803983435342525447474430167398340504412444749036071442672 | None | ||
| edn_genbits | 24250240894784326997003435583875986095485065082120448741383980553237110293672 | None | ||
| edn_stress_all | 46449344061828133047542487197336686399354532263358121634894065599375377244517 | None | ||
| edn_stress_all_with_rand_reset | 4407733416828249698933652186098679725073122124962168120910288678890151413626 | None | ||
| edn_intr | 64850312361819630266271190979483194776819777174574314881816401235534253357524 | None | ||
| edn_alert | 115590059705256093486769639902544642057955246289411240790434752766023048550527 | None | ||
| edn_err | 69160502819425427501224577665971736012752659738223927723749069051211338911876 | None | ||
| edn_disable | 100956592703548150855100255157609283301947118115299439637906258040173076583037 | None | ||
| edn_disable_auto_req_mode | 77800679057294231832179213057447280121043739245247198780343589496775390407750 | None | ||
| edn_sec_cm | 105809457845781960452511452806944247142099723786799625259373007715226740883097 | None | ||
| edn_alert_test | 80641345768301624630898173043157869734668013554094025895337176904073322500875 | None | ||
| edn_tl_errors | 18004763284203701600197810209795430572019014571298537765440210405208433992935 | None | ||
| edn_tl_intg_err | 32729899713566721392940527489214072291718569096724109805303452678503810616046 | None | ||
| edn_intr_test | 21393470778660460825924184765999147454910286082375373218608779251867728397723 | None | ||
| edn_csr_hw_reset | 17787767167257972199596205965150816079895038898607635106816138177450816740162 | None | ||
| edn_csr_rw | 58840021455415569415370280965301568895129923388191255291291872651934249603168 | None | ||
| edn_csr_bit_bash | 27118484906944629353547963862152044224927673604091118572230848109263940257562 | None | ||
| edn_csr_aliasing | 81198733327003178164067314909027451057033020443660688247934231443148513215230 | None | ||
| edn_same_csr_outstanding | 88412939094508562809427610736056106302110090078725731697984341526232108511254 | None | ||
| edn_csr_mem_rw_with_rand_reset | 56436222724114589793685326754382863961576913298369169782909646431480822529500 | None | ||
| edn | None | None | ||
| edn | None | None | ||