Simulation Results: hmac

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.69 %
  • code
  • 96.08 %
  • assert
  • 95.86 %
  • func
  • 29.13 %
  • block
  • 97.64 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.000s 174.630us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 126.473us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 60.353us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.000s 2145.176us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 461.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 3.000s 87.607us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 60.353us 1 1 100.00
hmac_csr_aliasing 6.000s 461.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 15.000s 4013.887us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 34.000s 2871.816us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 182.000s 9880.479us 1 1 100.00
hmac_test_sha384_vectors 22.000s 982.221us 1 1 100.00
hmac_test_sha512_vectors 362.000s 48571.924us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 306.010us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 388.162us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 1136.823us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.000s 147.452us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 371.000s 33094.731us 1 1 100.00
error 1 1 100.00
hmac_error 20.000s 2645.443us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 14.000s 885.526us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.000s 174.630us 1 1 100.00
hmac_long_msg 15.000s 4013.887us 1 1 100.00
hmac_back_pressure 34.000s 2871.816us 1 1 100.00
hmac_datapath_stress 371.000s 33094.731us 1 1 100.00
hmac_burst_wr 6.000s 147.452us 1 1 100.00
hmac_stress_all 161.000s 65730.305us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.000s 174.630us 1 1 100.00
hmac_long_msg 15.000s 4013.887us 1 1 100.00
hmac_back_pressure 34.000s 2871.816us 1 1 100.00
hmac_datapath_stress 371.000s 33094.731us 1 1 100.00
hmac_wipe_secret 14.000s 885.526us 1 1 100.00
hmac_test_sha256_vectors 182.000s 9880.479us 1 1 100.00
hmac_test_sha384_vectors 22.000s 982.221us 1 1 100.00
hmac_test_sha512_vectors 362.000s 48571.924us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 306.010us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 388.162us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 1136.823us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.000s 174.630us 1 1 100.00
hmac_long_msg 15.000s 4013.887us 1 1 100.00
hmac_back_pressure 34.000s 2871.816us 1 1 100.00
hmac_datapath_stress 371.000s 33094.731us 1 1 100.00
hmac_burst_wr 6.000s 147.452us 1 1 100.00
hmac_error 20.000s 2645.443us 1 1 100.00
hmac_wipe_secret 14.000s 885.526us 1 1 100.00
hmac_test_sha256_vectors 182.000s 9880.479us 1 1 100.00
hmac_test_sha384_vectors 22.000s 982.221us 1 1 100.00
hmac_test_sha512_vectors 362.000s 48571.924us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 306.010us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 388.162us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 1136.823us 1 1 100.00
hmac_stress_all 161.000s 65730.305us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 161.000s 65730.305us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 13.099us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 50.589us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 314.434us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 314.434us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 126.473us 1 1 100.00
hmac_csr_rw 1.000s 60.353us 1 1 100.00
hmac_csr_aliasing 6.000s 461.824us 1 1 100.00
hmac_same_csr_outstanding 3.000s 998.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 126.473us 1 1 100.00
hmac_csr_rw 1.000s 60.353us 1 1 100.00
hmac_csr_aliasing 6.000s 461.824us 1 1 100.00
hmac_same_csr_outstanding 3.000s 998.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 501.113us 1 1 100.00
hmac_tl_intg_err 3.000s 185.019us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 185.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.000s 174.630us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.000s 116.947us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 62.000s 8443.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 57.683us 1 1 100.00