Simulation Results: i2c

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.13 %
  • code
  • 90.10 %
  • assert
  • 96.41 %
  • func
  • 80.89 %
  • block
  • 96.30 %
  • line
  • 95.73 %
  • branch
  • 93.40 %
  • toggle
  • 87.10 %
  • FSM
  • 84.17 %
Validation stages
V1
100.00%
V2
80.49%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 241.000s 7809.124us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 8.000s 1230.580us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 17.820us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.000s 20.670us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.000s 516.403us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 2.000s 48.182us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 84.084us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.000s 20.670us 1 1 100.00
i2c_csr_aliasing 2.000s 48.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.000s 27.022us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 2.000s 37.065us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 57.000s 28443.828us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.000s 44.299us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 0.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 1433.000s 1989.331us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 2.000s 84.137us 1 1 100.00
i2c_host_fifo_fmt_empty 14.000s 1343.143us 1 1 100.00
i2c_host_fifo_reset_rx 3.000s 543.948us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 786.000s 7156.803us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 14.000s 872.599us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 3.000s 150.858us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 3.000s 547.968us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 0.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 6.000s 1525.159us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 18.000s 1608.877us 1 1 100.00
i2c_target_intr_smoke 5.000s 2845.383us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.000s 407.182us 1 1 100.00
i2c_target_fifo_reset_tx 2.000s 237.159us 1 1 100.00
target_fifo_full 2 3 66.67
i2c_target_stress_wr 0.000s 0.000us 0 1 0.00
i2c_target_stress_rd 18.000s 1608.877us 1 1 100.00
i2c_target_intr_stress_wr 1746.000s 13220.829us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 6.000s 4102.748us 1 1 100.00
target_clock_stretch 0 1 0.00
i2c_target_stretch 0.000s 0.000us 0 1 0.00
bad_address 1 1 100.00
i2c_target_bad_addr 5.000s 852.474us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 3.000s 707.943us 1 1 100.00
target_fifo_watermark 1 2 50.00
i2c_target_fifo_watermarks_acq 3.000s 1974.025us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.000s 11.018us 0 1 0.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 57.000s 28443.828us 1 1 100.00
i2c_host_perf_precise 2560.000s 6058.789us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 14.000s 872.599us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.000s 109.998us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 5.000s 1095.414us 1 1 100.00
i2c_target_nack_acqfull_addr 4.000s 498.624us 1 1 100.00
i2c_target_nack_txstretch 3.000s 244.022us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 8.000s 2297.506us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 3.000s 420.449us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 1.000s 44.794us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 1.000s 61.225us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.000s 128.707us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.000s 128.707us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 17.820us 1 1 100.00
i2c_csr_rw 1.000s 20.670us 1 1 100.00
i2c_csr_aliasing 2.000s 48.182us 1 1 100.00
i2c_same_csr_outstanding 2.000s 47.730us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 17.820us 1 1 100.00
i2c_csr_rw 1.000s 20.670us 1 1 100.00
i2c_csr_aliasing 2.000s 48.182us 1 1 100.00
i2c_same_csr_outstanding 2.000s 47.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.000s 589.092us 1 1 100.00
i2c_sec_cm 2.000s 110.477us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.000s 589.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 7.000s 1759.931us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 3.000s 346.955us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 9.000s 1022.157us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
i2c_host_fifo_watermark 101150971080828584056246027829200761667187575161266676671760738399146378630304 None
Job timed out after 60 minutes
i2c_target_stress_wr 47481841331683518628684811192062972018169029337773830864630297814801414937052 None
Job timed out after 60 minutes
i2c_target_stretch 61750951075165092172720471771138113123467608434630742222791342842382047186164 None
Job timed out after 60 minutes
i2c_target_stress_all 110135442859497219140378025701719350663975863622814821371432061235140714752440 None
Job timed out after 60 minutes
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 6196621864439170946490240109676044764365488530025546048891840237149327992080 92
UVM_ERROR @ 27022475 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 27022475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 7407082923314220025543144443281222753653906610559285208271600603979780905811 96
UVM_ERROR @ 37065313 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 37065313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 27276074426586359918326706520335144499673866333649576062081158920175326733923 93
UVM_ERROR @ 547968055 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 547968055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 40665729305702705400964359857035681107064122054046036781204029728603172957953 87
UVM_ERROR @ 346954677 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 48 [0x30])
UVM_INFO @ 346954677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 11417958579417159223810063603784087101547764284370255262482142016444119649549 125
UVM_ERROR @ 1759930741 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1759930741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 95218222775190871462550614761719804156187905191313041444888739524354096684091 95
UVM_ERROR @ 1022157114 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1022157114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:847) [i2c_target_fifo_watermarks_tx_vseq] Check failed (std::randomize(num_data_total) with {num_data_total inside {[cfg.min_data : cfg.max_data]};}) Randomization failed!
i2c_target_fifo_watermarks_tx 76635969677817597929650962115503379775636509185509760868166308370358777273885 110
UVM_FATAL @ 11017616 ps: (i2c_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.i2c_target_fifo_watermarks_tx_vseq] Check failed (std::randomize(num_data_total) with {num_data_total inside {[cfg.min_data : cfg.max_data]};}) Randomization failed!
UVM_INFO @ 11017616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---