Simulation Results: lc_ctrl/volatile_unlock_disabled

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.93 %
  • code
  • 92.89 %
  • assert
  • 95.97 %
  • func
  • 86.94 %
  • block
  • 96.66 %
  • line
  • 97.29 %
  • branch
  • 91.49 %
  • toggle
  • 87.53 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 223.684us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 241.252us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 20.321us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 28.934us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.922us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 26.402us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 20.321us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 660.086us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.000s 4344.014us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 19.470us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 117.309us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 1082.846us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_prog_failure 3.000s 117.309us 1 1 100.00
lc_ctrl_errors 8.000s 1082.846us 1 1 100.00
lc_ctrl_security_escalation 6.000s 661.152us 1 1 100.00
lc_ctrl_jtag_state_failure 19.000s 2126.216us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 146.682us 1 1 100.00
lc_ctrl_jtag_errors 28.000s 6342.028us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.000s 794.470us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.000s 1263.806us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 146.682us 1 1 100.00
lc_ctrl_jtag_errors 28.000s 6342.028us 1 1 100.00
lc_ctrl_jtag_access 3.000s 540.939us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 1218.525us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 806.050us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 50.484us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 602.901us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 874.463us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 17.161us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 97.656us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 274.725us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 893.141us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 55.376us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 17.000s 4433.599us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 25.073us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 430.183us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 430.183us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 241.252us 1 1 100.00
lc_ctrl_csr_rw 2.000s 20.321us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.922us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 194.345us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 241.252us 1 1 100.00
lc_ctrl_csr_rw 2.000s 20.321us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.922us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 194.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 1062.818us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 1062.818us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.000s 4344.014us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 6774.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 235.025us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 661.152us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 660.086us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.000s 1263.806us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 273.955us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 273.955us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 1314.432us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 315.023us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 315.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 30.000s 6437.777us 1 1 100.00