Simulation Results: lc_ctrl/volatile_unlock_enabled

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.17 %
  • code
  • 92.79 %
  • assert
  • 95.82 %
  • func
  • 87.90 %
  • block
  • 96.62 %
  • line
  • 97.27 %
  • branch
  • 91.42 %
  • toggle
  • 87.22 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 88.743us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 38.735us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 55.526us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 68.770us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 20.562us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 21.504us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 55.526us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 20.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 182.021us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.000s 363.621us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 12.981us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 19.235us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 407.460us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_prog_failure 2.000s 19.235us 1 1 100.00
lc_ctrl_errors 5.000s 407.460us 1 1 100.00
lc_ctrl_security_escalation 7.000s 750.495us 1 1 100.00
lc_ctrl_jtag_state_failure 31.000s 3570.254us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 4975.132us 1 1 100.00
lc_ctrl_jtag_errors 33.000s 8485.840us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 716.972us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 251.282us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 3140.155us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 397.645us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 157.583us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 391.661us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 399.084us 1 1 100.00
lc_ctrl_jtag_smoke 3.000s 192.973us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 371.534us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 4975.132us 1 1 100.00
lc_ctrl_jtag_errors 33.000s 8485.840us 1 1 100.00
lc_ctrl_jtag_access 4.000s 250.753us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.000s 1207.567us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 616.177us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 27.796us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 71.000s 19784.703us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 15.420us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 135.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 135.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 38.735us 1 1 100.00
lc_ctrl_csr_rw 2.000s 55.526us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 20.562us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 23.639us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 38.735us 1 1 100.00
lc_ctrl_csr_rw 2.000s 55.526us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 20.562us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 23.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 3.000s 108.718us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 108.718us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.000s 363.621us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 3.000s 158.164us 1 1 100.00
lc_ctrl_sec_cm 5.000s 462.041us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 750.495us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 182.021us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 371.534us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 357.717us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 357.717us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 360.049us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 612.889us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 612.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 31.000s 14710.647us 1 1 100.00