| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
92.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 14.000s | 194.184us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 15.475us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 3.000s | 15.936us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 5.000s | 34.325us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 3.000s | 68.681us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 6.000s | 67.579us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 3.000s | 15.936us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 3.000s | 68.681us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 106.000s | 18116.724us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 23.000s | 705.809us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 29.000s | 386.987us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 45.000s | 189.073us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 74.000s | 607.683us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 23.000s | 156.350us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 12.000s | 49.642us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 6.000s | 13.612us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 11.000s | 26.958us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 4.000s | 49.671us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 3.000s | 50.281us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 1058.490us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 1058.490us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 15.475us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 15.936us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 3.000s | 68.681us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 41.220us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 15.475us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 15.936us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 3.000s | 68.681us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 41.220us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 7.000s | 52.266us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 68.990us | 1 | 1 | 100.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 6.000s | 24.408us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 9.000s | 67.201us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 11.000s | 69.671us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 6.000s | 19.681us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 6.000s | 26.097us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 5.000s | 12.311us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 0 | 1 | 0.00 | |||
| otbn_partial_wipe | 5.000s | 3.532us | 0 | 1 | 0.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| otbn_tl_intg_err | 10.000s | 122.108us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 23.000s | 93.717us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 14.000s | 194.184us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 7.000s | 68.990us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 7.000s | 52.266us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 10.000s | 122.108us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 12.000s | 49.642us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 7.000s | 52.266us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 68.990us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 13.612us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 6.000s | 26.097us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 7.000s | 52.266us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 68.990us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 13.612us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 6.000s | 26.097us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 12.000s | 49.642us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 7.000s | 52.266us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 68.990us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 13.612us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 6.000s | 26.097us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 6.000s | 16.742us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 7.000s | 238.695us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 29.000s | 382.899us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 29.000s | 382.899us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 8.000s | 73.623us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 9.000s | 215.549us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 0 | 1 | 0.00 | |||
| otbn_stack_addr_integ_chk | 6.000s | 8.810us | 0 | 1 | 0.00 | |
| sec_cm_call_stack_addr_integrity | 0 | 1 | 0.00 | |||
| otbn_stack_addr_integ_chk | 6.000s | 8.810us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 6.000s | 44.070us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 74.000s | 607.683us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 10.000s | 23.741us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 14.000s | 50.755us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 98.000s | 1980.044us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 281.000s | 4939.634us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 8.000s | 225.794us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| otbn_stress_all_with_rand_reset | 19387954664314059611089374569988694165256261922627938158481177377647476942649 | 431 |
UVM_ERROR @ 4939634016 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4939634016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed | ||||
| otbn_stack_addr_integ_chk | 80427823760312027718064965889679188292755188503506347874421804555260603277987 | 117 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8809886 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 8809886 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 8809886 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8809886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status | ||||
| otbn_partial_wipe | 75372980326581472378577157188464383978499366023419073617731835784069145881951 | 114 |
UVM_ERROR @ 3532024 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (0 [0x0] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 3532024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|