Simulation Results

Simulation Results: rv_dm/use_dmi_interface

31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.35 %

code
74.48 %

assert
95.11 %

func
92.46 %

block
89.63 %

line
89.47 %

branch
71.87 %

toggle
75.86 %

FSM
60.71 %

Validation stages

V1		96.30%
V2		69.57%
V2S		85.71%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	30.000s	2660.853us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	242.567us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	32.000s	1122.572us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	63.000s	41701.162us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	34.000s	1422.914us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	33.000s	4719.093us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	34.000s	2353.670us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	49.000s	42854.236us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	229.000s	176406.620us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	29.000s	470.848us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	259.153us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	738.657us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	28.000s	268.759us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	29.000s	161.756us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	30.000s	362.200us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	29.000s	78.308us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	29.000s	303.558us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	29.000s	470.848us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	29.000s	208.384us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	271.116us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	738.657us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	45.747us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	34.000s	379.251us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	33.000s	88.060us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	73.000s	19574.480us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	64.000s	14177.289us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	32.000s	136.582us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	64.000s	14177.289us	1	1	100.00
	rv_dm_csr_rw	33.000s	88.060us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	51.935us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	32.000s	68.214us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	30.000s	2660.853us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	417.282us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	30.000s	504.728us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	32.000s	525.512us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	30.000s	1611.189us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	196.000s	300000.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	523.000s	300000.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	627.000s	300000.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	556.000s	300000.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	29.000s	432.355us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	31.000s	5478.495us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	925.975us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	30.000s	222.098us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	34.000s	7242.531us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	72.000s	5353.407us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	189.567us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	0.000s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	139.528us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	34.000s	1655.387us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	34.000s	1655.387us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	64.000s	14177.289us	1	1	100.00
	rv_dm_csr_hw_reset	34.000s	379.251us	1	1	100.00
	rv_dm_csr_rw	33.000s	88.060us	1	1	100.00
	rv_dm_same_csr_outstanding	37.000s	494.503us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	64.000s	14177.289us	1	1	100.00
	rv_dm_csr_hw_reset	34.000s	379.251us	1	1	100.00
	rv_dm_csr_rw	33.000s	88.060us	1	1	100.00
	rv_dm_same_csr_outstanding	37.000s	494.503us	1	1	100.00

V2S

6/7 passed

85.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	30.000s	1165.505us	1	1	100.00
	rv_dm_tl_intg_err	38.000s	2427.030us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	38.000s	2427.030us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	5478.495us	1	1	100.00
	rv_dm_debug_disabled	29.000s	202.106us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	5478.495us	1	1	100.00
	rv_dm_debug_disabled	29.000s	202.106us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	30.000s	2660.853us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				0	1	0.00
	rv_dm_buffered_enable	31.000s	490.688us	0	1	0.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	73.899us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	73.899us	1	1	100.00
sec_cm_exec_ctrl_mubi				0	1	0.00
	rv_dm_buffered_enable	31.000s	490.688us	0	1	0.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	35.000s	2229.543us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	347.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	70660819667063935340240608587958795796318967669300685412283550525071242014885	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	24518752736398102210049957238720201682513734480338853214115588143598012810752	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	6313788988132620912202054155134939397798437164869062553492925954018609279771	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	21638304008562435563352951011219996723799360135844302247782530451427197708894	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	22962584258786774532711212696386759970800863063874757958706452307065961268033	87	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	69280388420244445801444841995985585956613981912852807562926179661579899024332	87	UVM_ERROR @ 268759320 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 268759320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	62629981649353711995882611128850650940223859032959584923740807548624613965998	87	UVM_ERROR @ 222097529 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 222097529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	8444490937614337453977281918265461563103905858746557723232582209575539251914	87	UVM_ERROR @ 432354874 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (383265685 [0x16d82b95] vs 0 [0x0]) UVM_INFO @ 432354874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])
	rv_dm_buffered_enable	33384644482100596019933165333211544374010332853586619461157074331709792921229	92	UVM_ERROR @ 490688496 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) UVM_INFO @ 490688496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	rv_dm_stress_all	16121308495675561169515366668287111217991859667376171078088953378748677305273	None	Job timed out after 180 minutes
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
	rv_dm_stress_all_with_rand_reset	16352065855706431887362849997646418953044003808223423186595655882057774821018	100	UVM_FATAL @ 2229542570 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done) UVM_INFO @ 2229542570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---