Simulation Results: rv_timer

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 128.437us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 14.372us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 16.105us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 304.915us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.418us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 21.515us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 16.105us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 7.000s 25348.637us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 3884.102us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 6.000s 4963.947us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 6.000s 4963.947us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 6.000s 4266.606us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 198.693us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 11.282us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 124.133us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 124.133us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 14.372us 1 1 100.00
rv_timer_csr_rw 1.000s 16.105us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.418us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 19.788us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 14.372us 1 1 100.00
rv_timer_csr_rw 1.000s 16.105us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.418us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 19.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 73.503us 1 1 100.00
rv_timer_tl_intg_err 2.000s 97.117us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 97.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 1.000s 32.341us 1 1 100.00
max_value 1 1 100.00
rv_timer_max 1.000s 27.764us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 30.000s 31806.592us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 13379270003184011498622852675660595961309546792297966697430662737380118259820 84
UVM_FATAL @ 25348636593 ps: (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2e028704) == 0x1
UVM_INFO @ 25348636593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---