Simulation Results

Simulation Results: spi_device/1r1w

31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
84.54 %

code
91.66 %

assert
94.64 %

func
67.32 %

block
98.36 %

line
98.79 %

branch
97.02 %

toggle
81.25 %

FSM
89.58 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	439.000s	41046.291us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	3.000s	81.416us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	2.000s	214.213us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	17.000s	5338.468us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	23.000s	1184.617us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	3.000s	114.181us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	2.000s	214.213us	1	1	100.00
	spi_device_csr_aliasing	23.000s	1184.617us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	2.000s	19.546us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	4.000s	249.433us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	2.000s	16.650us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	2.000s	1.531us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	1.000s	6.611us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	2.000s	50.877us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	2.000s	50.877us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	9.000s	6525.616us	1	1	100.00
	spi_device_tpm_sts_read	2.000s	112.159us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	9.000s	394.402us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	5.000s	252.189us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	5.000s	772.228us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	5.000s	772.228us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	11.000s	809.115us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	11.000s	809.115us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	11.000s	809.115us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	11.000s	809.115us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	11.000s	809.115us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	3.000s	92.049us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	6.000s	1092.944us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	6.000s	1092.944us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	6.000s	1092.944us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	57.000s	4411.266us	1	1	100.00
	spi_device_read_buffer_direct	11.000s	681.938us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	6.000s	1092.944us	1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	36.000s	10438.507us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	7.000s	2888.097us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	7.000s	2888.097us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	439.000s	41046.291us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	330.000s	28812.853us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	593.000s	562334.192us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	2.000s	37.644us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	1.000s	24.409us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	5.000s	692.657us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	5.000s	692.657us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	3.000s	81.416us	1	1	100.00
	spi_device_csr_rw	2.000s	214.213us	1	1	100.00
	spi_device_csr_aliasing	23.000s	1184.617us	1	1	100.00
	spi_device_same_csr_outstanding	6.000s	226.833us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	3.000s	81.416us	1	1	100.00
	spi_device_csr_rw	2.000s	214.213us	1	1	100.00
	spi_device_csr_aliasing	23.000s	1184.617us	1	1	100.00
	spi_device_same_csr_outstanding	6.000s	226.833us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_sec_cm	3.000s	65.747us	1	1	100.00
	spi_device_tl_intg_err	13.000s	2318.649us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	13.000s	2318.649us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	208.000s	53335.754us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
	spi_device_mem_parity	81746597081359311623220406897855220223778688348981899307125649882141882085299	87	UVM_ERROR @ 1041515 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[46] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) UVM_ERROR @ 1041515 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) ERROR: VHPI NOTFOUND Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[942] not found within the scope . UVM_ERROR @ 1041515 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[942] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	87819238943221725942593745508772647323565000341061668204649337228508997030307	85	UVM_ERROR @ 4330226 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9c51fa [100111000101000111111010] vs 0x0 [0]) UVM_ERROR @ 4347226 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x194114 [110010100000100010100] vs 0x0 [0]) UVM_ERROR @ 4427226 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc0ea43 [110000001110101001000011] vs 0x0 [0]) UVM_ERROR @ 4509226 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x921ae4 [100100100001101011100100] vs 0x0 [0]) UVM_ERROR @ 4514226 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4faaf2 [10011111010101011110010] vs 0x0 [0])