Simulation Results: sram_ctrl/main

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.11 %
  • code
  • 82.38 %
  • assert
  • 95.54 %
  • func
  • 92.40 %
  • block
  • 92.87 %
  • line
  • 93.59 %
  • branch
  • 87.03 %
  • toggle
  • 82.24 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 63.000s 6311.461us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 13.398us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.421us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 46.500us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 163.612us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 2473.775us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.421us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 163.612us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 177.000s 21879.724us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 98.000s 4866.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 610.000s 41625.433us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 142.000s 10440.054us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1318.000s 127030.134us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 111.000s 13188.766us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 59885.618us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 440.000s 41676.174us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 17.000s 1120.477us 1 1 100.00
sram_ctrl_partial_access_b2b 276.000s 101338.018us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 5.000s 2746.937us 0 1 0.00
sram_ctrl_throughput_w_partial_write 27.000s 805.858us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 667.245us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 515.000s 24336.890us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 346.513us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2812.000s 240603.748us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.112us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 622.669us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 622.669us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 13.398us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.421us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 163.612us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.628us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 13.398us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.421us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 163.612us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 7653.024us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 1.000s 29.968us 0 1 0.00
sram_ctrl_tl_intg_err 2.000s 294.832us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 1.000s 29.968us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 294.832us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 515.000s 24336.890us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 515.000s 24336.890us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.421us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 440.000s 41676.174us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 440.000s 41676.174us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 440.000s 41676.174us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 59885.618us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 673.581us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 7653.024us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 824.075us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 63.000s 6311.461us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 63.000s 6311.461us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 440.000s 41676.174us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 1.000s 29.968us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 59885.618us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 1.000s 29.968us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 29.968us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 63.000s 6311.461us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 29.968us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 32.000s 3495.633us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 82077290909432389564628995644809055118305322540576082856880875370059513660421 102
UVM_FATAL @ 2746936960 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 2746936960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 25482854946885852078824421066432073501924088835890889200616128717729693284611 102
UVM_FATAL @ 667245398 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 667245398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 14082540000375041565069308310810551041533673787630576853181956918541829250007 95
UVM_ERROR @ 29968262 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 29968262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---