Simulation Results: sram_ctrl/ret

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.14 %
  • code
  • 83.90 %
  • assert
  • 95.37 %
  • func
  • 94.16 %
  • block
  • 94.69 %
  • line
  • 95.69 %
  • branch
  • 90.62 %
  • toggle
  • 82.61 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 37.000s 6565.400us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 22.140us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.398us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 246.265us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.719us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 39.660us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 33.398us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.719us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 562.575us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 174.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 1006.000s 67796.751us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 170.000s 4820.758us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 55.000s 9050.561us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 305.000s 14027.184us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.000s 1424.878us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 517.000s 38447.149us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 14.000s 4110.325us 1 1 100.00
sram_ctrl_partial_access_b2b 341.000s 21446.326us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 2.000s 35.432us 0 1 0.00
sram_ctrl_throughput_w_partial_write 57.000s 227.210us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 62.372us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 337.000s 8140.026us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 77.356us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2800.000s 83574.727us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 16.890us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 34.143us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 34.143us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 22.140us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.398us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.719us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 18.786us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 22.140us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.398us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.719us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 18.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 305.748us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 1.000s 11.365us 0 1 0.00
sram_ctrl_tl_intg_err 2.000s 693.189us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 1.000s 11.365us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 693.189us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 337.000s 8140.026us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 337.000s 8140.026us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.398us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 517.000s 38447.149us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 517.000s 38447.149us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 517.000s 38447.149us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.000s 1424.878us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 68.857us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 305.748us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 33.478us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 37.000s 6565.400us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 37.000s 6565.400us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 517.000s 38447.149us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 1.000s 11.365us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.000s 1424.878us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 1.000s 11.365us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 11.365us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 37.000s 6565.400us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 1.000s 11.365us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 594.321us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 2056335496931899608008737254560236672582980776363789749242559142469235953710 102
UVM_FATAL @ 35431762 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 35431762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 18939242971909420413390109787271349712699862667791096799844830729891004071590 102
UVM_FATAL @ 62372180 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 62372180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 44740153163469837170093827887530706523796276953270503302031026711563355883153 90
UVM_ERROR @ 11365362 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 11365362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---