Simulation Results: uart

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.73 %
  • code
  • 96.39 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 88.53 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 725.838us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 16.062us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 12.261us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 34.070us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 63.740us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 45.315us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 12.261us 1 1 100.00
uart_csr_aliasing 1.000s 63.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 13.000s 89634.275us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 725.838us 1 1 100.00
uart_tx_rx 13.000s 89634.275us 1 1 100.00
parity_error 2 2 100.00
uart_intr 93.000s 66090.587us 1 1 100.00
uart_rx_parity_err 23.000s 34992.383us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 13.000s 89634.275us 1 1 100.00
uart_intr 93.000s 66090.587us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 203.000s 123960.454us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 42.000s 123081.241us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 23.000s 16396.644us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 93.000s 66090.587us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 93.000s 66090.587us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 93.000s 66090.587us 1 1 100.00
perf 1 1 100.00
uart_perf 412.000s 17033.786us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 4113.238us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 4113.238us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 9.000s 28899.302us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 3352.288us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 792.575us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.000s 7257.334us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 45.000s 68777.926us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 252.000s 52857.456us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 12.128us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 11.895us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 48.134us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 48.134us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.062us 1 1 100.00
uart_csr_rw 1.000s 12.261us 1 1 100.00
uart_csr_aliasing 1.000s 63.740us 1 1 100.00
uart_same_csr_outstanding 1.000s 46.315us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.062us 1 1 100.00
uart_csr_rw 1.000s 12.261us 1 1 100.00
uart_csr_aliasing 1.000s 63.740us 1 1 100.00
uart_same_csr_outstanding 1.000s 46.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 123.811us 1 1 100.00
uart_tl_intg_err 2.000s 479.996us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 479.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 13.000s 1602.948us 1 1 100.00